Critical Path Tube Redundancy for Power Minimization in CNFET Circuits With Variations

Tube redundancy and correlation has been proposed to increase the functional yield of CNFET-based circuits under CNT variations. However, adding redundant-CNTs is associated with increased power and sometimes increased area. The impact of CNT correlation on CNFET-based circuit performance also remains unexplored. Adding redundancy to all transistors in a circuit was considered in many works. In this paper, we propose adding an optimized number of redundant tubes only to transistors on critical paths. The optimized number of redundant-CNTs is pre-calculated for a desired functional yield. We show that this restricted redundancy retains the improved delay-limited yield achieved in circuits with redundant-CNTs added to all transistors. Moreover, this limited redundancy also reduces power dissipation without exceeding the allowed delay degradation. To ensure redundant tubes are added to all transistors on all critical paths which can emerge in all fabricated circuits due to CNT variations, those paths must first be identified. We propose an efficient method to identify all the critical paths that can exist in the presence of CNT variations. With uncorrelated-CNFETs, our approach reduces the average power increase by 7.8% as compared to all-transistor redundancy. Results also show an improvement in critical path delay by 15–20% and up to 10% reduction in allowed delay-degradation. To examine the influence of tube correlation on CNFET-based circuit performance, two correlated-CNFET standard-cell layouts are evaluated. An average increase of 1.8X in critical path delay variation due to CNFET correlation is noticed in a set of ISCAS’85 benchmarks.