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The actively body-bias controlled (ABC) silicon-on-insulator (SOI) technology is described that has controlled the body biases without an area penalty and increase of the parasitic gate capacitance. The studies have shown the enhancement of the speed performance and the reduction of the variation for the ABC SOI technology.

A procedure is proposed for obtaining identification (ID) numbers using polycrystalline silicon (poly-Si) thin-film transistors (TFT).

The drive current on floating and body-fixed partially depleted (PD) SOI MOSFETs was evaluated in detail. It was revealed for the first time that the limitation of the drive current for floating partially depleted (Pd) SOI MOSFETs is due to a larger body effect because of higher channel impurity doping.

It has been demonstrated that the sub-100-nm vertical MOSFET can be fabricated with a lot of advantages. In addition to the advantages mentioned, vertical n-MOS transistors process technologies are readily available.

An 0.18-micrometer silicon-on-insulator (SOI) comlementary metal-oxide semiconductor that relies on hybrid-trench isolation with a high-resistivity substrate is described. Its feasibility for embedded RF/analog applications is discussed.

The effect of a gate-all-around thin-film transistor (GAT) with a lightly doped drain structure on the reduction of the off-current is studied. The off-current of the GAT is found to be almost the same as that of a single-gate TFT with an LDD structure although the GAT's channel area is about twice as big as that of the SGT. The suppression mechanism of the individual performance variations in the GAT is also investigated by thinning the channel poly-Si.

An asymmetric memory cell, a single-bit-line static random access memory cell, was designed using a complementary thin-film transistor (C-TFT). The structure of the C-TFT was constructed with n-channel and p-channel TFTs which share the same gate. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4 micrometer design rules. The cell was found to be capable of stable read and write operations with further decreases cell size.

Examination of the substrate-bias effect in body-tied silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors showed that a transistor body that is reverse-biased results in the complete depletion of the body and the transistor's release from the substrate-bias effect. The study also found that the level of the source-drain voltage is high for both reverse-bias and zero bias. A body-tied SOI configuration is proposed as a potential candidate for random logic circuits.

A study was conducted to characterize a unique static random access memory cell called complementary-switch cell. The cell, which integrates a single-bit-line architecture, features a C-switch that combines a bn-channel bulk transistor and a p-channel TFT. It also supports low-voltage operation for read and write operation and is capable of minimizing cell size more effectively than standard cells.

The idea that the field shield (FS) isolation technology can actually suppress the delay time instability over a wide input frequency range is demonstrated. Device simulation was used to analyze the transitional change of the body potential of silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor during inverter operation and to investigate how the body resistance influence the delay time instability. Results showed that FS isolation can be used to suppress the frequency-dependent instability for practical deep submicron SOI circuits.

A novel approach of assessing threshold voltage shift variation due to negative-bias temperature stress in poly-crystalline silicon thin-film transistors (Si tft) has been devised. The technique centers around poly-silicon boundary and poly-Si/SiO2 interface negative-bias temperature stress. Evidence from the chemical reaction indicates that two types of hydrogenated dangling bonds exist. The technique is applicable to poly-crystalline Si tft device development.

Dynamic random access memory cells using a vertical phi-shape transistor (V-Phi-T) cell effectively process information of 1 Gbit and above. The V-Phi-T cell is an efficient vertical MOSFET with a 4F(super 2) size, where F is the minimum feature size. The V-Phi-T cell forms by the penetration of a gate electrode followed by the formation of a channel plug within the penetrating hole. The electrical properties of the cell improve with scaling down.

Fluorine ion implementation is used to develop high-reliability and high-performing thin film resistors (TFTs). Putting fluorine into the TFT's gate poly-Si caused a Vth shift, due to generation of negative charges in the gate oxide. The negative charges are due to implantation raising the ON current and cutting the leakage current. Fluorine implantation also generated high immunity to -BT stress and time dependent dielectric breakdown in the gate oxide.

Deals with a study which showed that floating-body effects cause the reduction of the saturation drive current in partially depleted silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFET). Analyses of drive current in SOI MOSFET; Analyses of short channel effect in SOI MOSFET; Details of the proposed high drive current device structure.

Discusses the proposed partial trench isolated (PTI) technology and silicon-on-insulated technology (SOI) which realize stable operation without circuit-layout modifications and additional process steps. Claims of being immune from floating-body effects; Details of the speed-performance improvement of PTI-SOI technology; Significance of PTI technology on SOI applications.