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This paper reports on improved AlGaN/GaN metal oxide semiconductor high-electron mobility transistors (MOS-HEMTs). TiO2 is used to form the dielectric and passivation layers. The TiO2 film is characterized using X-ray photoemission spectroscopy (XPS), Raman spectroscopy, and transmission electron microscopy (TEM). The quality of the gate oxide is improved by annealing at 300 °C in N2. Experimental results indicate that the annealed MOS structure effectively reduces the gate leakage current. The high performance of the annealed MOS-HEMTs and their stable operation at elevated temperatures up to 450 K is demonstrated. Furthermore, annealing improves their output power characteristics. [ABSTRACT FROM AUTHOR]

In this paper, a Two-Channel AlGaN/GaN structure of Metal-Oxide Semiconductor High-Electron Mobility Transistors (MOS-HEMTs) with TiO2 gate dielectric is presented. Also, we have examined its electrical characteristics, such as band structure, the electric field, and electric potential. The proposed device's performance is always affected by the effects of self-heating. The performance of the proposed transistor has been evaluated by considering thermal models in Silvaco TCAD software. The simulation results show that the self-heating has significant effects on the response of the proposed device. We conclude that the drain current at VDS = 2 V is reduced by about 16%. Also, the mobility of electrons in both created channels of the structure can significantly reduce (nearly 34%). Therefore, it can be found that the self-heating effect leads to the degradation of the proposed transistor performance. In this paper, the self-heating effects of the MOS-HEMT transistor are reduced by using 6H-SiC material as a passive layer and placing a field plate near the gate. The results confirm that the breakdown voltage and drain current have increased by more than 78 and 20%, respectively. [ABSTRACT FROM AUTHOR]

We demonstrated the performance of an Al2O3/SiO2 stack layer AlGaN/GaN metal–oxide semiconductor (MOS) high-electron-mobility transistor (HEMT) combined with a dual surface treatment that used tetramethylammonium hydroxide (TMAH) and hydrochloric acid (HCl) with post-gate annealing (PGA) modulation at 400 °C for 10 min. A remarkable reduction in the reverse gate leakage current (IG) up to 1.5 × 10 − 12   A / mm (@ VG = −12 V) was observed in the stack layer MOS-HEMT due to the combined treatment. The performance of the dual surface-treated MOS–HEMT was significantly improved, particularly in terms of hysteresis, gate leakage, and subthreshold characteristics, with optimized gate annealing treatment. In addition, an organized gate leakage conduction mechanism in the AlGaN/GaN MOS–HEMT with the Al2O3/SiO2 stack gate dielectric layer was investigated before and after gate annealing treatment and compared with the conventional Schottky gate. The conduction mechanism in the reverse gate bias was Poole–Frankel emission for the Schottky-gate HEMT and the MOS–HEMT before annealing. The dominant conduction mechanism was ohmic/Poole-Frankel at low/medium forward bias. Meanwhile, gate leakage was governed by the hopping conduction mechanism in the MOS–HEMT without gate annealing modulation at a higher forward bias. After post-gate annealing (PGA) treatment, however, the leakage conduction mechanism was dominated by trap-assisted tunneling at the low to medium forward bias region and by Fowler–Nordheim tunneling at the higher forward bias region. Moreover, a decent product of maximum oscillation frequency and gate length (fmax × LG) was found to reach 27.16 GHz∙µm for the stack layer MOS–HEMT with PGA modulation. The dual surface-treated Al2O3/SiO2 stack layer MOS–HEMT with PGA modulation exhibited decent performance with an IDMAX of 720 mA/mm, a peak extrinsic transconductance (GMMAX) of 120 mS/mm, a threshold voltage (VTH) of −4.8 V, a higher ION/IOFF ratio of approximately 1.2 × 10 9 , a subthreshold swing of 82 mV/dec, and a cutoff frequency(ft)/maximum frequency of (fmax) of 7.5/13.58 GHz. [ABSTRACT FROM AUTHOR]

An AlGaN/GaN MOS-HEMT (metal oxide semiconductor–high electron mobility transistor)-based dosimeter has been proposed to demonstrate and evaluate the impact of absorbed doses of radiations by virtue of interface trap charges at the interface of SiO2/AlGaN. The effect of various radiation doses induced (Nt = − 3 × 1012cm−2 to + 3 × 1012cm−2) has been studied in terms of various electrical parameters, such as channel conductance (gd), drain current (Ids), transconductance (gm), and threshold voltage(Vth). Variations in the drain current and channel potential, and a significant shift in the threshold voltage, have been observed. Threshold voltage and drain current increase proportionally to the radiation dose induced due to the addition of positive charges on the surface, leading to increased charge carrier concentration in two-dimensional electron gas (2DEG). Modifying the electron mobility/or density by the effects of induced radiation affects the functionality of the 2DEG-based device. The maximum changes in output conductance, drain current, threshold voltage change, drain-on sensitivity, and transconductance observed for the proposed sensor are 69%, 0.073 A, 593 mV, 0.314, and 0.018 S, respectively. The effects of variation in gate length on the threshold voltage sensitivity and sensor drain current have been studied. [ABSTRACT FROM AUTHOR]

This paper reports on improved AlGaN/GaN metal oxide semiconductor high-electron mobility transistors (MOS-HEMTs). TiO2 is used to form the dielectric and passivation layers. The TiO2 film is characterized using X-ray photoemission spectroscopy (XPS), Raman spectroscopy, and transmission electron microscopy (TEM). The quality of the gate oxide is improved by annealing at 300 °C in N2. Experimental results indicate that the annealed MOS structure effectively reduces the gate leakage current. The high performance of the annealed MOS-HEMTs and their stable operation at elevated temperatures up to 450 K is demonstrated. Furthermore, annealing improves their output power characteristics.

Comparative analysis of a Symmetric Heterojunction Underlap Double Gate (U-DG) GaN/AlGaN Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) on varying the effective capacitance by using different oxide materials on source and drain sides, and determination of optimum length of oxides for the superior device performance has been presented in this work. This paper shows a detailed performance analysis of the Analog Figure of Merits (FoMs) like variation of Drain Current (IDS), Transconductance (gm), Output Resistance (R0), Intrinsic Gain (gmR0), RF FoMs like cut-off frequency (fT), maximum frequency of oscillation (fMAX), gate to source resistance (RGS), gate to drain resistance (RGD), gate to drain capacitance(CGD), gate to source capacitance (CGS) and total gate capacitance (CGG) using Non-Quasi-Static (NQS) approach. Power analysis includes Output power (Pout), Gain in dBm and power output efficiency (POE) have been studied. Studies reveal that the device with higher dielectric material towards source side shows superior performance. On subsequently changing the proportion of two oxides in a layer by varying length, it is observed that as the proportion of oxide increases the device demonstrates more desirable Analog and RF characteristics while best power performance is obtained from device with equal lengths of HfO2 and SiO2. [ABSTRACT FROM AUTHOR]

We present a performance enhancement evaluation of n + doped graded InGaN drain/source region-based HfO2/InAlN/AlN/GaN/AlN on SiC metal-oxide-semiconductor high electron mobility transistor (MOS-HEMTs) with a T-shaped gate. Impact on the device characteristics with the inclusion of a HfO2 surface passivation layer and an AlN buffer layer in the MOS-HEMT structure as a performance booster has been analyzed for the HEMT device with 30 nm gate length using Silvaco ATLAS TCAD. The proposed MOS-HEMT exhibits an outstanding performance, with an enhanced power gain cut-off frequency (fmax) of 366 GHz, a current gain cut-off frequency (ft) of 426 GHz, and a off-state breakdown voltage (Vbr) of 81 V. The high-k (high permittivity) HfO2 based metal oxide semiconductor HEMT device experiences a low off-state gate leakage current (Ig ~ 10−11A/mm) and a high Ion/Ioff ratio of 109. The InAlN/GaN/AlN heterostructures demonstrate improved two-dimensional electron gas (2DEG ~ 5.3 × 1013 cm−2), carrier mobility (μ) of 1256 Cm2/V-s and drain current density of (Ids) 2.7 A/mm. A large signal analysis performed at 30 GHz yielded a maximum of 28% power-added efficiency. The high JFoM of 34.506 THz V (Johnson Figure of Merit = ft × Vbr) and (ft.fmax)1/2 of 394.86 GHz indicate the potential applicability of the HfO2/InAlN/GaN MOS-HEMTs in high-frequency and high-power applications.

We demonstrated the performance of an Al2O3/SiO2 stack layer AlGaN/GaN metal–oxide semiconductor (MOS) high-electron-mobility transistor (HEMT) combined with a dual surface treatment that used tetramethylammonium hydroxide (TMAH) and hydrochloric acid (HCl) with post-gate annealing (PGA) modulation at 400 °C for 10 min. A remarkable reduction in the reverse gate leakage current (IG) up to 1.5×10−12 A/mm (@ VG = −12 V) was observed in the stack layer MOS-HEMT due to the combined treatment. The performance of the dual surface-treated MOS–HEMT was significantly improved, particularly in terms of hysteresis, gate leakage, and subthreshold characteristics, with optimized gate annealing treatment. In addition, an organized gate leakage conduction mechanism in the AlGaN/GaN MOS–HEMT with the Al2O3/SiO2 stack gate dielectric layer was investigated before and after gate annealing treatment and compared with the conventional Schottky gate. The conduction mechanism in the reverse gate bias was Poole–Frankel emission for the Schottky-gate HEMT and the MOS–HEMT before annealing. The dominant conduction mechanism was ohmic/Poole-Frankel at low/medium forward bias. Meanwhile, gate leakage was governed by the hopping conduction mechanism in the MOS–HEMT without gate annealing modulation at a higher forward bias. After post-gate annealing (PGA) treatment, however, the leakage conduction mechanism was dominated by trap-assisted tunneling at the low to medium forward bias region and by Fowler–Nordheim tunneling at the higher forward bias region. Moreover, a decent product of maximum oscillation frequency and gate length (fmax × LG) was found to reach 27.16 GHz∙µm for the stack layer MOS–HEMT with PGA modulation. The dual surface-treated Al2O3/SiO2 stack layer MOS–HEMT with PGA modulation exhibited decent performance with an IDMAX of 720 mA/mm, a peak extrinsic transconductance (GMMAX) of 120 mS/mm, a threshold voltage (VTH) of −4.8 V, a higher ION/IOFF ratio of approximately 1.2×109, a subthreshold swing of 82 mV/dec, and a cutoff frequency(ft)/maximum frequency of (fmax) of 7.5/13.58 GHz.

The device performance of AlGaN/InGaN/GaN Double Heterostructure Metal-Oxide-Semiconductor High Electron Mobility Transistor (DH MOS-HEMT) upon using 10 nm thick Zirconium Dioxide (ZrO2) as dielectric is studied here. Oxide dielectrics play an important role in forming Two-Dimensional Electron Gas (2DEG). An analytical model is proposed for evaluating the charge density, carrier concentration, drain current, transconductance, and gate capacitance of the device. ZrO2 based DH MOS-HEMTs display exceptional performances such as maximum drain current density (IDmax) and transconductance (gmmax) in comparison to InGaN based HEMTs. Due to the high-quality 2DEG ace between ZrO2 and the AlGaN barrier layer, the MOS-HEMT demonstrates excellent carrier concentrations and gate capacitances. Also, electrostatic analysis at various interfaces is carried out and the impact of InGaN layer thickness over the 2DEG enhancement is investigated. An exceptional agreement is formed between the experimental results from the literature and the produced outputs. Incorporating a strong high-k dielectric material like ZrO2 results in an effective leakage suppression in the range of 10 – 7 mA/mm. The results show that the device could be a feasible solution for both high-power switching and microwave applications. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model of AlGaN/GaN MOS-HEMT based pH sensor for the first time to determine pH of different electrolyte solutions. Gouy-chapman stern model has been used to calculate the surface charge density. The results obtained using analytical model have been verified and show good agreement with the simulated results. Cavity length, thickness of AlGaN barrier layer and Al composition have been optimized to improve the sensitivity of the device. It has been observed that the drain current and threshold voltage decreases with increase in pH of the electrolytic solutions. Proposed AlGaN/GaN MOS-HEMT sensor demonstrate a quick response to the pH changes. The maximum drain-on-sensitivity of the device is 132mA/mm-pH. Surface potential and threshold voltage sensitivity of 0.95mV/pH and 950mV/pH respectively have been obtained which is much higher than the Nernstian limit(59.2mV/pH). [ABSTRACT FROM AUTHOR]

C-MOSHEMT (Circular-Metal Oxide Semiconductor High Electron Mobility Transistor) has been modeled, fabricated and sensitivity analysis has been done for pH detection application for the first time. Prototype model of the sensor has been developed considering a ring gate structure. The perimeter of the gate inner ring is taken as the gate length and a gate width of $100~\mu \text{m}$ has been used to plot normalized device characteristics. Advantage of C-MOSHEMT over L-MOSHEMT (linear MOSHEMT) is that the area available for sensing increases and process cost and complexity involved remains low from the fabrication point of view. The overall fabrication cost and process overheads reduce with elimination of the mesa isolation etch. ALD (Atomic Layer Deposition) deposited Al2O3 used as the gate oxide and passivation scheme in the device design ensures higher sensitivities along with current collapse free device operation. Analytical model along with experimental analysis have been done using 3 standard buffer pH samples, pH=4, 7, and 9.2. The devices fabricated showcase a maximum sensitivity of 1.74 mA/pH and 1.86 mA/pH when gate lengths ($\text{L}_{G}$) of $3~\mu \text{m}$ and $5\mu \text{m}$ are considered. Further, the model and the physical detection results are compared and contrasted to study the strengths and weaknesses of the model developed. It has been observed that as sensing area is doubled, the sensitivity increases by 41% which can be attributed to the discreteness of charge distribution on the sensing surface. [ABSTRACT FROM AUTHOR]

This work reports the fabrication, characterization and testing for pH sensitivity of dielectric modulated MOS-HEMT(Metal oxide semiconductor- high electron mobility transistor) devices for bio-sensing applications. The primary aim here is to develop high sensing devices for bio-detections. The oxide based gate area is used in ensuring the device performance through pH detection done prior to packaging and metal probing. Device parameters; gate length LG, gate width WG, gate spacing from source-drain ends, LSG and LGD have been varied to investigate the effect on pH sensitivity. The HEMT stack with AlN spacer has been grown through MOCVD (Metal-Organic Chemical Vapor Deposition) technique with no intentional doping on Si (silicon) substrate. Commercial buffer samples for pH values of 4, 7, 9.2 have been used to test the devices using drop casting technique. Drain current (ID) based sensitivity analysis shows that the device having ($\text{L}_{{\text {SG}}} = 4\,\,\mu \text{m}$ , $\text{L}_{{\text {G}}} = 3\,\,\mu \text{m}$ and $\text{L}_{{\text {GD}}} = 18\,\,\mu \text{m}$) exhibits a maximum sensitivity of 3.361 mA/pH. The devices exhibit exemplary performance when device dimensions meet the following constraints i.e. LSG: minimum, LG: moderate and LGD > 2*LSG. Average sensitivities attained is in the range 1.69 mA/pH for a device with $\text{L}_{{\text {G}}} = 3\,\,\mu \text{m}$ , $\text{L}_{{\text {SG}}} = 2\,\,\mu \text{m}$ and $\text{L}_{{\text {GD}}} = 6\,\,\mu \text{m}$. [ABSTRACT FROM AUTHOR]

AlGaN/GaN metal-oxide semiconductor high electron mobility transistors (MOS-HEMTs) with undoped ferroelectric HfO2 have been investigated. Annealing is often a critical step for improving the quality of as-deposited amorphous gate oxides. Thermal treatment of HfO2 gate dielectric, however, is known to degrade the oxide/nitride interface due to the formation of Ga-containing oxide. In this work, the undoped HfO2 gate dielectric was spike-annealed at 600 °C after the film was deposited by atomic layer deposition to improve the ferroelectricity without degrading the interface. As a result, the subthreshold slope of AlGaN/GaN MOS-HEMTs close to 60 mV/dec and on/off ratio>109 were achieved. These results suggest optimizing the HfO2/nitride interface can be a critical step towards a low-loss high-power switching device.

In this paper, we have demonstrated the optimized device performance in the Γ-shaped gate AlGaN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) by incorporating aluminum into atomic layer deposited (ALD) HfO2 and comparing it with the commonly used HfO2 gate dielectric with the N2 surface plasma treatment. The inclusion of Al in the HfO2 increased the crystalline temperature (~1000 °C) of hafnium aluminate (HfAlOX) and kept the material in the amorphous stage even at very high annealing temperature (>800 °C), which subsequently improved the device performance. The gate leakage current (IG) was significantly reduced with the increasing post deposition annealing (PDA) temperature from 300 to 600 °C in HfAlOX-based MOS-HEMT, compared to the HfO2-based device. In comparison with HfO2 gate dielectric, the interface state density (Dit) can be reduced significantly using HfAlOX due to the effective passivation of the dangling bond. The greater band offset of the HfAlOX than HfO2 reduces the tunneling current through the gate dielectric at room temperature (RT), which resulted in the lower IG in Γ-gate HfAlOX MOS-HEMT. Moreover, IG was reduced more than one order of magnitude in HfAlOX MOS-HEMT by the N2 surface plasma treatment, due to reduction of N2 vacancies which were created by ICP dry etching. The N2 plasma treated Γ-shaped gate HfAlOX-based MOS-HEMT exhibited a decent performance with IDMAX of 870 mA/mm, GMMAX of 118 mS/mm, threshold voltage (VTH) of −3.55 V, higher ION/IOFF ratio of approximately 1.8 × 109, subthreshold slope (SS) of 90 mV/dec, and a high VBR of 195 V with reduced gate leakage current of 1.3 × 10−10 A/mm.

This work attempts to analyses the effect of oxide layer thickness on the performance of Underlap Double Gate (DG) AlInN/GaN Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) device. The device has a hetrostructure of lattice-matched wideband AlInN and narrowband GaN layers in the channel and Al2O3 in the oxide layer. The effect of Al2O3 thickness on device performance is analyzed using Sentaurus TCAD simulation software. The hydrodynamic model used in the simulation is calibrated with the previously published experimental result. A comprehensive, quantitative investigation of transfer characteristics, output characteristics, transconductance (gm), transconductance generation factor (TGF), threshold voltage (Vt), subthreshold slope (SS) and drain induced barrier lowering (DIBL) is done for varying Al2O3 thickness. As oxide thickness increases drain current ID, SS and DIBL increases. On the contrary, increase in oxide thickness results in decrease of gm, TGF and Vt decreases. These results demonstrate the feasibility of obtaining desired set of device properties by tuning the oxide thickness. [ABSTRACT FROM AUTHOR]

Surface passivation is critically important to improve the current collapse and the overall device performance in metal-oxide semiconductor high-electron mobility transistors (MOS-HEMTs) and, thus, their reliability. In this paper, we demonstrate the surface passivation effects in AlGaN/AlN/GaN-based MOS-HEMTs using ultraviolet-ozone (UV/O3) plasma treatment prior to SiO2 -gate dielectric deposition. X-ray photoelectron spectroscopy (XPS) was used to verify the improved passivation of the GaN surface. The threshold voltage (VTH) of the MOS-HEMT was shifted towards positive due to the band bending at the SiO2/GaN interface by UV/O3 surface treatment. In addition, the device performance, especially the current collapse, hysteresis, and 1/f characteristics, was further significantly improved with an additional 15 nm thick hafnium silicate (HfSiOX) passivation layer after the gate metallization. Due to combined effects of the UV/O3 plasma treatment and HfSiOX surface passivation, the magnitude of the interface trap density was effectively reduced, which further improved the current collapse significantly in SiO2-MOS-HEMT to 0.6% from 10%. The UV/O3-surface-modified, HfSiOX-passivated MOS-HEMT exhibited a decent performance, with IDMAX of 655 mA/mm, GMMAX of 116 mS/mm, higher ION/IOFF ratio of approximately 107, and subthreshold swing of 85 mV/dec with significantly reduced gate leakage current (IG) of 9.1 ×10−10 A/mm.

Abstract: In this paper, the effects of gate induced noise for a gate recessed enhancement‐mode GaN‐based metal‐oxide‐semiconductor high electron mobility transistor (MOS‐HEMT) is investigated. To analyze this, a surface potential–based compact model for gate induced noise is developed. The model is validated by comparing with TCAD device simulation results as well as with the available experimental data of GaN HEMT and MOS‐HEMT having different gate lengths and widths from the literature. With the help of the developed model, the effect of oxide thickness on different noise sources is investigated by considering all high‐frequency noise sources including the shot noise resulted from gate leakage current. The effects of gate leakage current on different technology dependent parameters such as oxide thickness and gate length are also investigated. A 2‐port noise equivalent circuit for GaN MOS‐HEMT is designed by considering all high‐frequency noise sources. The different noise parameter models are developed from the Y parameters of the 2‐port noise equivalent circuit and compared with available experimental data of GaN HEMT and MOS‐HEMT from literature. The impact of gate induced noise on all noise parameters is also investigated. [ABSTRACT FROM AUTHOR]

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression MOS field plate is deployed on the etched upper GaN channel layer after a barrier fully recess process, leading to a low reverse OFF-state leakage current of −20 nA/mm (at −100 V). The drain metal is deployed adjacent to the MOS field plate, contacting the upper MOS-channel and lower heterojunction channel from the sidewall. A metal-2DEG Schottky contact with a low turn-ON voltage of 0.5 V is achieved. Since the lower channel (below the MOS field plate) is separated from the etched surface of upper GaN channel layer, a high-conductivity MOS-gated channel with a sheet resistance of 806 $\Omega$ /Square is obtained. The device exhibits a threshold voltage of +0.6 V (at $10~\mu \text{A}$ /mm and +1.9 V from linear extrapolation) and an ON-resistance of ~18 $\Omega {\cdot} \text {mm}$. Besides, a high forward (and reverse) breakdown voltage of 790 V (and −656 V, all at $10~\mu \text{A}$ /mm) is achieved. [ABSTRACT FROM AUTHOR]

III-N surface polarization compensating charge referred here to as ‘surface donors’ (SD) was analyzed in Al 2 O 3 /AlGaN/GaN metal-oxide-semiconductor (MOS) heterojunctions using scaled oxide films grown by metal-organic chemical vapor deposition at 600 °C. We systematically investigated impact of HCl pre-treatment prior to oxide deposition and post-deposition annealing (PDA) at 700 °C. SD density was reduced down to 1.9 × 10 13 cm −2 by skipping HCl pre-treatment step as compared to 3.3 × 10 13 cm −2 for structures with HCl pre-treatment followed by PDA. The nature and origin of SD was then analyzed based on the correlation between electrical, micro-structural, and chemical properties of the Al 2 O 3 /GaN interfaces with different SD density ( N SD ). From the comparison between distributions of interface traps of MOS heterojunction with different N SD , it is demonstrated that SD cannot be attributed to interface trapped charge. Instead, variation in the integrity of the GaO x interlayer confirmed by X-ray photoelectron spectroscopy is well correlated with N SD , indicating SD may be formed by border traps at the Al 2 O 3 /GaO x interface. [ABSTRACT FROM AUTHOR]

In this paper, a compact channel noise model for gate recessed enhancement mode GaN based MOS-HEMT which is valid for all regions of operation is proposed. The compact noise model consists of high frequency thermal noise and low frequency flicker noise. The drain current, which is one of the most important parameters for compact noise model is developed by incorporating interface and oxide traps, mobility degradation due to vertical electric field, velocity saturation effect and self-heating effect. The flicker noise model is derived by considering mobility and carrier fluctuation due to traps present in both oxide and interface layer. The thermal noise and flicker noise models are validated by comparing the results with TCAD simulation and experimental results from literature respectively. Effect of thermal and flicker noise power spectral density (PSD) variation with different oxide thickness has also been analyzed. [ABSTRACT FROM AUTHOR]

In this paper the drain current low-frequency noise (LFN) of E-mode GaN MOS-HEMT is investigated for different gate insulators such as SiO 2 , Al 2 O 3 /Ga 2 O 3 /GdO 3 , HfO 2 /SiO 2 , La 2 O 3 /SiO 2 and HfO 2 with different trap densities by IFM based TCAD simulation. In order to analyze this an analytical model of drain current low frequency noise is developed. The model is developed by considering 2DEG carrier fluctuations, mobility fluctuations and the effects of 2DEG charge carrier fluctuations on the mobility. In the study of different gate insulators it is observed that carrier fluctuation is the dominant low frequency noise source and the non-uniform exponential distribution is critical to explain LFN behavior, so the analytical model is developed by considering uniform distribution of trap density. The model is validated with available experimental data from literature. The effect of total number of traps and gate length scaling on this low frequency noise due to different gate dielectrics is also investigated. [ABSTRACT FROM AUTHOR]

Systematic designs to achieve normally-off operation and improved device performance for Al 0.26 Ga 0.74 N/AlN/GaN high electron mobility transistors (HEMTs) grown on a Si substrate are investigated in this work. The step-by-step approach includes: (1) devising a thin AlGaN/AlN composite barrier, (2) introducing fluoride ions within the active region by using CF 4 plasma treatment, (3) growing the Al 2 O 3 oxide passivation layers within gate-drain/source regions by using a cost-effective ozone water oxidization technique, and (4) integrating a metal-oxide-semiconductor gate (MOS-gate) design with high- k Al 2 O 3 gate dielectric. Devices with four different evolutionary gate structures have been compared and studied. Variations of threshold voltage ( V th ), Hooge coefficients ( α H ), maximum drain-source current density ( I DS, max ), maximum extrinsic transconductance ( g m, max ), gate-voltage swing ( GVS ) linearity, two-terminal gate-drain breakdown/turn-on voltages ( BV GD / V on ), on/off current ratio ( I on / I off ), and high-temperature characteristics up to 450 K are also investigated. [ABSTRACT FROM AUTHOR]

The letter reports normally-off device characteristics of Al 0.26 Ga 0.74 N/AlN/GaN oxide-passivated high electron mobility transistors (HEMTs) and metal-oxide-semiconductor HEMTs (MOS-HEMTs) grown on a Si substrate. Al 2 O 3 was formed as the surface passivation oxide or gate dielectric on a thin AlGaN barrier layer by using a cost-effective ozone water oxidization technique. CF 4 plasma was used to enable normally-off operation. For the gate dimensions of 1×100 µm 2 , the present oxide-passivated HEMT and MOS-HEMT (a control Schottky-gate HEMT) have demonstrated superior on/off-current ratio ( I on / I off ) of 2.5×10 6 and 1×10 7 (3.9×10 3 ), maximum extrinsic transconductance ( g m, max ) of 154 and 175 (120) mS/mm, maximum drain-source current density ( I DS, max ) of 312 and 349 (300) mA/mm, two-terminal gate-drain breakdown voltage ( BV GD ) of −80 and −140 (−36) V, turn-on voltage ( V on ) of 1.2 and 1.3 (1) V, and three-terminal on-state breakdown voltage ( BV DS ) of 93 and 109 (48) V. Excellent BV GD and BV DS enhancements of 122% (288%) and 94% (127%) are achieved in the present oxide-passivated HEMT (MOS-HEMT) design. [ABSTRACT FROM AUTHOR]

AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) on Si substrates with TiO2 gate dielectrics are fabricated. The dc and power characteristics of AlGaN/GaN MOS-HEMTs are compared with that of metal-gate HEMTs fabricated on the same material. The gate leakage current for the MOS-HFET is more than two orders of magnitude smaller than for the HEMT at 300 K. The high-speed performance potential of the MOS-HEMT with an f T = 10.44 GHz and an fmax = 13.8 GHz is confirmed. The MOS-HEMT shows higher extrinsic transconductance, breakdown voltage, high-frequency and power characteristics relative to the HEMT. Furthermore, experimental results reveal that this studied MOS-HEMT is feasible for use at high temperatures. [ABSTRACT FROM AUTHOR]

We demonstrate for the first time that a single-crystalline epitaxial MgxCa1-xO film can be deposited on gallium nitride (GaN) by atomic layer deposition (ALD). By adjusting the ratio between the amounts of Mg and Ca in the film, a lattice matched MgxCa1-xO/GaN(0001) interface can be achieved with low interfacial defect density. High-resolution X-ray diffraction (XRD) shows that the lattice parameter of this ternary oxide nearly obeys Vegard's law. An atomically sharp interface from cross-sectional transmission electron microscopy (TEM) confirmed the high quality of the epitaxy. High-temperature capacitance-voltage characterization showed that the film with composition Mg0.25Ca0.75O has the lowest interfacial defect density. With this optimal oxide composition, a Mg0.25Ca0.75O/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility (MOS-HEMT) device was fabricated. An ultrahigh on/off ratio of 1012 and a near ideal SS of 62 mV/dec were achieved with this device. [ABSTRACT FROM AUTHOR]

In this work, the threshold instability in E-mode GaN MOS-HEMTs was investigated. In particular, the shift of VTH as a function of the applied positive gate voltage during device characterization was monitored, resulting in positive VTH shifts up to 1 V. A complete VTH recovery required more than one day of unbiased storage, but a partial recovery of the observed VTH shift was observed after few seconds. These results could be related to different positions of trap states: fast states, localized at the dielectric/GaN interface and slow states, the traps inside the dielectric layer. Moreover, VTH shift of 0.2 and 0.8 V for fast and slow states, respectively, was obtained. To gain insight into the physical mechanism involved in the observed phenomena, numerical simulation were also carried out. A VTH shift was obtained adding the interface states. Moreover, three different distributions of traps were compared. In particular, the concentration of filled traps was monitored to understand the impact of the distribution on the electrical behaviour. An increment in filled trap concentration at the increasing of the applied VGS, which in turns correlates with experimentally evaluated device behaviour, was obtained if the distribution of traps states is also above the GaN conduction band energy. [ABSTRACT FROM AUTHOR]

GaN-based devices are seen as ideal candidates for power-switching applications. For the acceptance of GaN-based devices by module designers, obtaining enhancement-mode (e-mode) behavior in GaN-based heterostructure field-effect transistors (HFETs) has long been in the focus. Although the gate-injection approach appears to be the most promising one to achieve e-mode devices, using a double heterostructure in conjunction with a gate insulator has still its advantages, such as steeper turn-ON characteristics and lower leakage currents. An analytical expression to predict the threshold voltage V\mathrm {th} for a given double heterostructure device has not yet been derived. Moreover, neither an evaluation of the tradeoff between V\mathrm {th} and ON-state resistance $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}} has been performed to date. This paper addresses these two aspects. We will show an analytical expression for a metal–insulator–semiconductor double HFET (MIS-DHFET), which in certain cases is also valid for the gate-injection transistor. On the basis of this, we will discuss the actual influence of the Al concentration in the backbarrier on V\mathrm th . We will further employ technology computer aided design (TCAD) device simulations to evaluate the impact on R{\text {ds},\mathrm {\scriptstyle {{ON}}}} when using MIS-DHFETs. It will be shown that by implementing a double heterostructure in MIS devices, it is possible to suppress the typically observed negative V\mathrm {th} –oxide thickness relationship while maintaining a constant $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ . [ABSTRACT FROM AUTHOR]

This work uncovers the potential benefit of AlInN/GaN underlap double-gate MOS-HEMT for RF and analog applications. The device channel consists of a lattice-matched wideband Al 0.83 In 0.17 N and narrowband GaN layers, along with high-K Al 2 O 3 as the gate dielectric. The 2D Sentaurus TCAD simulation is done using the hydrodynamic model and interface traps are considered. The simulation model was calibrated with the previously reported experimental result. A comprehensive, quantitative investigation of key analog and RF figures-of-merits (FOMs) is done for a wide range of gate length ( L g ), underlap length ( L un ) and barrier thickness ( T B ). Scaling of L g and L un leads to increase in the drain current ( I d ), transconductance ( g m ), cutoff frequency ( f T ) and max frequency ( f max ) but, at the expense of the reduced transconductance generation factor ( g m /I d ), gain and output resistance ( R o ). Large improvement in almost all analog and RF FOMs was observed for scaled L g and L un . Devices with thinner barrier thickness exhibited improved g m , TGF, R o , f T and f max . Simulations have revealed a very high drain current of 5.26 mA/μm, peak g m of 5.34 mS/μm, and a maximum gain of 47 dB. The peak values of f T and f max , extracted from two port Y-parameters, were found to be 786 GHz and 832 GHz, respectively for highly scaled device. These results demonstrate the potential of AlInN/GaN underlap MOS-HEMT for high power and high-frequency applications. [ABSTRACT FROM AUTHOR]

We report on a low specific on-resistance ( R on,sp ) of 3.58 mΩ-cm 2 and a high breakdown voltage of 1.4 kV in a CMOS-compatible AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT). The MOS-HEMT is on a Si substrate and uses TaN electrodes and a HfO 2 -gate insulator. The sputtered TaN – a substitute for Au that has low resistivity, high work function, and thermal stability – was applied at room temperature to the gate, source, and drain. In order to obtain a low R on,sp and high breakdown voltage, sputtering power and post-annealing temperature were optimized by measuring the characteristics of TaN. Using optimized conditions, a sputtering power of 50 W, and an annealing temperature of 880 °C, we successfully achieved a high on/off current ratio of 6 × 10 9 for the proposed AlGaN/GaN MOS-HEMT at a gate–drain distance of 10 μm. These results indicate that the TaN process is a promising technique for power-switching GaN devices with CMOS compatibility. [ABSTRACT FROM AUTHOR]

One of the key challenges for the adoption of gallium nitride (GaN)-based heterostructure field effect transistors (HFETs) in power-switching applications is obtaining enhancement mode behavior. A large variety of methods have been applied to shift the threshold voltage V\mathrm {th} of HFETs. However, most of the time, approaches were discussed individually, neglecting the effects of combinations. Hence, in this paper, a comprehensive study of four different approaches to shift V\mathrm {th} well into the positive range is presented. We show the effects of different gate metallizations, of a backbarrier, of a gate oxide, and of a gate recess. Each approach is discussed individually, and special focus is on the insulator/semiconductor interface, which is apparently different with and without gate recess. The final device exhibits a V\mathrm {th} of +2.3 V, which is shown to be stable when applying OFF-state stress during dynamic characterization. [ABSTRACT FROM AUTHOR]

In the present paper, we propose a novel device structure by introducing a source field-plated AlGaN/GaN in the metal oxide Semiconductor high electron mobility transistors (MOS-HEMT) structure having a relatively short gate length and short gate-to-drain distances. The 2D breakdown analysis is performed using Sentaurus TCAD simulator. The effects of gate to drain distance ( L g d ), source field plate length ( L f p ) and passivation layer thickness ( t p ) on breakdown voltage (BV) is analyzed. The simulations are done using the drift–diffusion (DD) model, which is calibrated/validated with the previously published experimental results. The breakdown voltage is observed to increase with increase in L f p and t p . Very high breakdown voltage of 752.8 V is obtained by optimizing the L f p to 3 µm and t p to 200 nm at a fixed gate to drain distance of 3.4 µm. The results show a great potential application of the ultra-thin HfAlO source field plated AlGaN/GaN MOS-HEMT to deliver high currents and power densities in high power microwave technologies. [ABSTRACT FROM AUTHOR]

The article presents the results of modelling and simulation of normally-off AlGaN/GaN MOS-HEMT transistors. The effect of the resistivity of the GaN:C layer, the channel mobility and the use of high-k dielectrics on the electrical characteristics of the transistor has been examined. It has been shown that a low leakage current of less than 10−6 A/mm can be achieved for the acceptor dopant concentration at the level of 5 X 10 15 cm−3. The limitation of the maximum on-state current due to the low carrier channel mobility has been shown. It has also been demonstrated that the use of HfO2, instead of SiO2, as a gate dielectric increases on-state current above 0.7A/mm and reduces the negative influence of the charge accumulated in the dielectric layer. [ABSTRACT FROM AUTHOR]

Composite HfO2/Al2O3-dielectric In0.2Ga0.8As/Al0.24Ga0.76As metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) by using RF sputtering/ozone water oxidization, respectively, are investigated. In comparison with a conventional Schottky-gate device on the same epitaxial structure, an Al2O3 liner was chemically formed for the present MOS-HEMT to improve interfacial quality and decrease gate leakages. Moreover, a high-k HfO2 layer was further deposited on the Al2O3 liner to enhance the gate modulation capability. The present MOS-HEMT with the devised HfO2/Al2O3 dielectric stack has demonstrated excellent switching characteristics, including superior subthreshold slope (S.S.) of 70mV/dec and high drain-source current (IDS) on-off ratio of up to 6 orders. Improved direct-current (DC), radio-frequency (RF), and high-temperature device performances of the present design are also comprehensively studied in this work. [ABSTRACT FROM AUTHOR]

This paper presents first results of a new high performance enhancement-mode (E-mode) gallium nitride (GaN) based metal-oxide semiconductor high electron mobility transistor (MOS-HEMT) that employs an ultrathin 3 nm aluminium gallium nitride (Al0.25G0.75aN) barrier layer and relies on an induced two dimensional electron gas (2DEG) for operation. Devices have been demonstrated on both sapphire and silicon substrates. Single finger devices on a sapphire substrate were fabricated using 10 nm and 20 nm, and on a silicon substrate using 30 nm of plasma enhanced chemical vapour-deposited (PECVD) silicon dioxide (SiO2) as the gate dielectric. They demonstrated threshold voltages of +3 V, +2 V, +0.8 V and very high maximum drain currents of over 620 mA/mm, 550 mA/mm and 450 mA/mm, respectively. These results show that the proposed device concept can be a building block for future power electronic devices. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Abstract: In this study, the rare earth erbium oxide (Er2O3) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t) of the MOS–HEMT were 125mV/decade and 4.3×1012 cm−2, respectively. The dielectric constant of the Er2O3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166V for the conventional HEMT to –196V for the Er2O3 MOS–HEMT. [Copyright &y& Elsevier]

Highlights: [•] MOS-HEMT device having lattice-matched Al0.83In0.17N and wideband GaN layers for body. [•] 2D Sentaurus TCAD hydrodynamic simulation model calibrated with experimental results. [•] As barrier thickness increases Id increases and delay decreases, but both DIBL and SS increases. [•] As barrier thickness reduces, increase in Cgg, gm , gm /Id and Ro is noticed. [•] Very high fT =668GHz and fmax =312GHz extracted from two port Y-parameters. [ABSTRACT FROM AUTHOR]

In this paper, we systematically study the positive gate leakage current in AlGaN/GaN metal-oxide-semiconductor high electron-mobility transistors (MOS-HEMTs) with HfO dielectric using atomic layer deposition (ALD). We observe that the incorporated nitrogen ions will improve the positive gate leakage current of devices obviously, but do not change the reverse gate leakage current. The passivation mechanism of nitrogen ions in oxygen vacancies in HfO is studied by first-principles calculations. It is shown that the gap states of HfO caused by oxygen vacancies increase the positive gate leakage current of MOS-HEMTs. Nitrogen ions passivate the gap states of HfO and decrease the positive gate leakage current but do not effect the reverse gate leakage current. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1mΩcm2 has been projected for a MOS channel length of 0.38μm. We also have assessed the impact of high-k gate dielectrics, such as Al2O3. In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects. [ABSTRACT FROM AUTHOR]

Abstract: Considerable on-state impact ionization and off-state tunneling leakages are the two principal drawbacks of InAs/AlSb HEMTs, which have a small bandgap and type-II band lineup. This work introduced a wide-bandgap high-k Al2O3 between the gate metal and semiconductor surface and successfully demonstrated DC and RF performance of the InAs/AlSb metal–oxide–semiconductor HEMTs (MOS-HEMTs). An MOS-HEMT device with a 2.0μm gate length yields DC performance of I DSS =286mA/mm and Gm =495mS/mm and RF performance of fT =10.1GHz and f MAX =19.9GHz. Compared with a conventional HEMT, gate leakage is reduced by one order and the marked dependence of drain current on gate bias in the deep subthreshold region is largely alleviated. [Copyright &y& Elsevier]

High‐frequency characteristics of Lg = 60 nm In0.7Ga0.3As MOS‐high‐electron‐mobility transistor (HEMTs) with a 3 nm aluminium oxide grown by atomic‐layer‐deposition is reported. Fabricated In0.7Ga0.3As MOS‐HEMTs with Lg = 60 nm exhibit subthreshold‐swing (SS) = 89 mV/dec., drain‐induced‐barrier‐lowering = 98 mV/V, gm_max = 1.1 mS/μm, fT = 187 GHz and fmax = 202 GHz at VDS = 0.5 V. The high‐frequency characteristics showed is the best balanced demonstration of fT and fmax in the buried‐channel indium gallium arsenide MOS‐HEMTs, revealing a strong potential of the buried‐channel design scheme for future high frequency, low‐noise and high‐performance logic applications. [ABSTRACT FROM AUTHOR]