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We propose a main mechanism of large valley splitting experimentally observed at the interface of buried oxide (BOX)/silicon-on-insulator (SOI) structures. Silicon metal-oxide-semiconductor field effect transistors fabricated on a SIMOX (001) substrate, which is a kind of the SOI substrate, that is annealed at high temperatures for a long time are known to exhibit large valley splitting, but the origin of this splitting has long been unknown. Extended zone effective-mass approximation predicts that strain significantly affects valley splitting. In this study, we analyzed valley splitting based on this theory and found that the shear strain along [110] of approximately 5% near the BOX interface is a promising source for large valley splitting. [ABSTRACT FROM AUTHOR]

The ultra-wide bandgap of gallium oxide provides a rich plethora of electrically active defects. Understanding and controlling such defects is of crucial importance in mature device processing. Deep-level transient spectroscopy is one of the most sensitive techniques for measuring electrically active defects in semiconductors and, hence, a key technique for progress toward gallium oxide-based components, including Schottky barrier diodes and field-effect transistors. However, deep-level transient spectroscopy does not provide chemical or configurational information about the defect signature and must, therefore, be combined with other experimental techniques or theoretical modeling to gain a deeper understanding of the defect physics. Here, we discuss the current status regarding the identification of electrically active defects in beta-phase gallium oxide, as observed by deep-level transient spectroscopy and supported by first-principles defect calculations based on the density functional theory. We also discuss the coordinated use of the experiment and theory as a powerful approach for studying electrically active defects and highlight some of the interesting but challenging issues related to the characterization and control of defects in this fascinating material. [ABSTRACT FROM AUTHOR]

This paper provides a comprehensive study of the impact of the gate recess depth (RD) on the GaN-on-Si MOS-HEMTs DC performances. IDS = f(VGS) and IDS = f(VDS) measurements are conducted at 25 and 150 °C, respectively, in forward and blocking modes. The gate recessed depth (50, 150, and 350 nm) is modulated by adjusting the plasma etching time, which is a critical step for improving the dielectric/GaN interface quality and the gate channel electron mobility. Three distinct regions can be defined separately: the bottom, the sidewall, and the corner region being the junction between the two previous regions. To assess the impact of gate recessed depth (RD) on the several mobilities around the gate cavity first, we applied our previous methodology allowing us to extract the bottom (μbot) and the entire sidewall region mobility (μT), without distinction from the corner. The mobility of the transverse region was found surprisingly to increase with deeper RD. To gain insight into the impact of the RD on this transverse section, a new extraction methodology is proposed to extract separately the gate corner (μcorner) and sidewall (μSW) mobility. These extractions show that the corner mobility is found to be reduced compared to the sidewall one (μcorner < μSW) evidencing the different weighting contributions over the transverse mobility. Moreover, these mobilities are found to be more degraded compared to the bottom one, highlighting the different contributions on the on-state resistance (RON). Indeed, the on-state resistance is lowered with the shallower RD due to the reduced sidewall resistance contribution (lower sidewall length) and despite the incremental contribution of the bottom resistance (larger effective gate length). However, the shallower RD shows an increase in the drain–source leakage current in reason of a lower gate electrostatic control. Technology Computer Aided Design (TCAD) simulations of the three RD morphologies are carried out to validate the experimental trends and the proposed methodology. [ABSTRACT FROM AUTHOR]

This study investigates the sensitive region and safe operation voltage of single-event burnout (SEB) in lateral depletion-mode Ga2O3 MOSFET devices via technology computer aided design simulation. Based on the distribution of the electric field, carrier concentration, and electron current density when SEB occurs, the radiation damage mechanism of SEB is proposed. The mechanism of SEB in Ga2O3 MOSFET was revealed to be the result of a unique structure without a PN junction within it, which possesses gate control ability and exerts a significant influence on the conduction of the depletion region. [ABSTRACT FROM AUTHOR]

A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs. [ABSTRACT FROM AUTHOR]

The performance of SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) degrades seriously after a period of continuous operation. To directly understand this issue, we conduct real-time time-dependent density functional theory (TDDFT) simulations on a series of nitrogen passivated SiC– SiO 2 interfaces to monitor the interaction between carriers and interface atoms. We find that the nitrogen passivation always leaves behind two local states near the VBM, which gives a chance to the strong interaction between channel carriers and C–N bonds, and finally results in the generation of C dangling bond defects. These processes are vividly presented and confirmed by the TDDFT simulation. Additionally, the results show that the new defects are more easily formed by the passivated C cluster than the passivated Si vacancy. These studies provide physical insights into the degradation mechanisms of working SiC MOSFETs, while simultaneously demonstrating the advantage of TDDFT as a crucial tool for investigating defect generation dynamics in semiconductor devices. [ABSTRACT FROM AUTHOR]

Negative differential resistance (NDR) is observed in various emerging electronic devices. As compared to the conventional silicon-based field effect transistor (FET), the NDR is widely investigated in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs. In this work, we study the NDR effect for the TMD-based metal-edge-contact MoS 2 double-gate FET with 10 nm channel length. The multiscale atomistic simulation is demonstrated for the lateral heterostructure of a metal–semiconductor–metal FET by density functional theory, maximally localized Wannier function tight-binding Hamiltonian, and non-equilibrium Green's function methods. The quantum transport model in the given lateral heterostructure resulted in NDR in a double-gate FET. Here, we focus on the NDR by the systematic study of the transmission spectrum of the metal-edge-contact MoS 2 channel FET and finally compare it with zero NDR ideal highly doped FET. The peak-to-valley ratio in the NDR response can be modulated with the change in the gate-to-source voltage and can be used to explore various future electronic applications. [ABSTRACT FROM AUTHOR]

This Perspective focuses on experimental and theoretical aspects of positron annihilation spectroscopy. This set of methods is highly suitable for identifying and quantifying vacancy-type defects in semiconductors and also allows for analyzing their physics characteristics. We present selected examples from the past decade, where the methods have been used for obtaining timely and useful insights into the defect-controlled phenomenon in narrow-gap (Ge, GaSb) and wide-gap (III-nitride, oxide) semiconductors. We also discuss possible future developments that may allow more detailed studies in novel semiconductor materials and devices with ever more complex lattice structures. [ABSTRACT FROM AUTHOR]

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices. [ABSTRACT FROM AUTHOR]

The effects of tensile strain and contact transmissivity on the performance limits of monolayer molybdenum disulfide ( MoS 2) nanoscale n-channel MOSFETs are studied using a semi-classical Monte Carlo method. Density functional theory calculations were performed to parametrize the electronic band structure of MoS 2 subject to tensile and shear strain. Tensile strain decreases the bandgap, increases the inter-valley band-edge energy separation between the light-mass K-valleys and heavier-mass Q-valleys, and decreases the K-valley effective mass in a way that depends on the direction and the amount of the applied strain. Biaxial tensile strain and uniaxial tensile strain along the x- or y-directions are found to have the largest effect. In bulk materials, low-field phonon-limited electron mobility is enhanced, peak and saturation drift velocities are increased, and high-field negative differential resistance becomes more pronounced. Both 200 and 15 nm gate length MoS 2 MOSFETs with end-contacts with ideal (unity) and more realistic (significantly sub-unity) contact interface transmissivity were simulated. These MoS 2 devices exhibited substantial sensitivity to strain with ideal contact transmissivity, and more so for the 15 nm quasi-ballistic device scale than 200 nm long-channel devices. However, the results showed much less strain sensitivity for devices with more realistic contact transmissivities, which may be good or bad depending on whether strain-insensitive or strain-sensitive performance is desired for a particular application and may be possible to modify with improved contact geometries. [ABSTRACT FROM AUTHOR]

The relocation of peripheral transistors from the front-end-of-line (FEOL) to the back-end-of-line (BEOL) in fabrication processes is of significant interest, as it allows for the introduction of novel functionality in the BEOL while providing additional die area in the FEOL. Oxide semiconductor-based transistors serve as attractive candidates for BEOL. Within these categories, In2O3 material is particularly notable; nonetheless, the excessive intrinsic carrier concentration poses a limitation on its broader applicability. Herein, the deposition of Hf-doped In2O3 (IHO) films via atomic layer deposition for the first time demonstrates an effective method for tuning the intrinsic carrier concentration, where the doping concentration plays a critical role in determine the properties of IHO films and all-oxide structure transistors with Au-free process. The all-oxide transistors with In2O3: HfO2 ratio of 10:1 exhibited optimal electrical properties, including high on-current with 249 µA, field-effect mobility of 13.4 cm2 V−1 s−1, and on/off ratio exceeding 106, and also achieved excellent stability under long time positive bias stress and negative bias stress. These findings suggest that this study not only introduces a straightforward and efficient approach to improve the properties of In2O3 material and transistors, but as well paves the way for development of all-oxide transistors and their integration into BEOL technology. [ABSTRACT FROM AUTHOR]

The formation of a two-dimensional electron gas (2DEG) at the GaN (0001)/AlN interface holds significant implications for GaN-based high-voltage and high-frequency (RF) devices. Due to the promising results provided by the addition of a thin layer of AlN in metal–oxide-semiconductor channel high-electron-mobility transistor devices, this interface can be found in both the access region and near the dielectric gate. Recent ab initio simulations shed light on the crucial role played by spontaneous and piezoelectric polarizations within polar GaN and AlN crystals in driving the formation of the 2DEG. This study explores the underlying mechanisms behind the 2DEG formation and investigates the impact of fixed charges and additional layers, like Al 2 O 3 , on the carrier concentration. Consistent with the literature, our findings highlight the predominant role of polarizations within III–V materials in the formation of the 2DEG. Moreover, we examine the influence of fixed charges on the AlN surface, revealing their ability to accumulate or deplete the 2DEG, while maintaining charge conservation through the emergence of a new two-dimensional charge gas on the AlN surface. Additionally, we explore the effects of incorporating a β -Al 2 O 3 crystal layer on the GaN/AlN structure, finding that the 2DEG's carrier density is reduced, yet not entirely eliminated, while a significant positive charge concentration at the AlN/Al 2 O 3 interface pins the Fermi level. This comprehensive investigation contributes to our understanding of microscopic phenomena in III–V heterostructures, paving the way for future advancements and applications in power electronics. [ABSTRACT FROM AUTHOR]

In this article, we use spatially modulated control fields to increase the four-wave mixing efficiency in a four-subband semiconductor asymmetric double quantum well, motivated by similar works in atomic systems. Using a simplified version of the propagation equations, we show analytically that for control fields with a constant amplitude and linearly varying mixing angles with the propagation distance, a conversion efficiency close to unity can be achieved even for relatively short propagation distances. Subsequently, we confirm these results by numerically simulating the full set of propagation equations. [ABSTRACT FROM AUTHOR]

To this day, trapezoidal defects are found in clusters and high counts in wafers representing the industry standard in terms of material quality being produced. This study sheds light on the nature, origin, behavior, and impact of this defect on device yield and reliability. Trapezoidal defects in 4H-SiC epitaxial layers were investigated by photoluminescence (PL) imaging, scanning electron microscopy (SEM), cathodoluminescence spectrum imaging (CLSI), SEM electron beam induced current (EBIC) imaging, and by transmission electron microscopy (TEM) observation. The bar-shaped stacking faults were identified by the PL and CL measurements with a peak emission wavelength of 420 and 450 nm. An optoelectronic behavioral study based on the recombination enhanced dislocation glide mechanism revealed how expanding dislocations and stacking faults interact with each other. Combining the luminescence and microscopy results, the nature of the stacking faults was identified as being a combination of Shockley-type and Frank-type stacking faults. The TEM analysis showed that these defects originate from the substrate and the stacking sequences of some of the faults were determined as (...2, 4, 2...) and (...2, 3, 2...) in the Zhdanov's notation by high-resolution TEM. The origin of this defect is speculated based on our results and previous reports. The EBIC imaging showed that the high density of SFs in these towers is a strong site of carrier recombination, which presumably has an impact on the transfer characteristics of SiC devices. Furthermore, these defects have shown to impact metal oxide semiconductor field effect transistors electrical performance via an increase in the on-state resistance depending on the coverage percentage of the tower of defects in the active area of the device. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) power devices are becoming central components in high voltage electronics. However, defects at interfaces and in the bulk continue to severely impact their reliability and performance. Here, we develop a charge pumping method to characterize SiC/SiO 2 interface defects in fully fabricated commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The method is then used to address spin states at the SiC/SiO 2 interface via charge pumping electrically detected magnetic resonance (CP-EDMR). We apply these methods to investigate the power MOSFET after electron irradiation over a dose range of 10 13 − 10 17 cm − 2 . We finally discuss CP-EDMR as a technique to interrogate spins during device operation for real-time monitoring of the device quality, performance, and degradation and as a probe for local magnetic fields. [ABSTRACT FROM AUTHOR]

Switching a silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor between inversion and accumulation with removed drain and grounded source terminals leads to defect-assisted carrier recombination and light emission. The energy spectrum of the emitted photons provides valuable information on the involved defects, located both at the 4H-SiC/ SiO 2 interface and in the 4H-SiC bulk. Here, we measured and analyzed the emitted light over a broad temperature range between 12 and 297 K. Our results reveal two local maxima in light intensity around 30 and 140 K. Most importantly, the local intensity maxima and the related temperatures correlate with both the overall recombination current and gate capacitance measurements. The spectral analysis allowed us to distinguish between recombinations occurring on 4H-SiC bulk defects and 4H-SiC/ SiO 2 interface-related defects. We explain an initial increase of light emission with decreasing temperature to competing non-radiative pathways with activation energies of 34 and 60 meV for SiC/ SiO 2 interface- and 4H-SiC bulk-related emissions, respectively. Based on an extensive literature review, we link the measured photon emission to donor–acceptor pair recombination, the EH 6 / 7 or the Z 1 / 2 defect centers. In addition to that, we could link a prominent peak at 2.915 eV to the L 1 line of the D 1 -center. Most importantly, we conducted our own ab initio simulations revealing that recombination via P bC -centers, previously identified with carbon dangling bonds at the 4H-SiC/ SiO 2 interface [Cottom et al., J. Appl. Phys. 124, 045302 (2018)], could also provide an explanation for the photon emission around 1.75 eV. Finally, our simulation of an interface-related silicon vacancy V Si , I reveals a radiative transition around 2.8 eV. [ABSTRACT FROM AUTHOR]

Understanding defect creation is central to efforts to comprehend gate dielectric breakdown in metal-oxide-semiconductor-field-effect-transistors (MOSFETs). While gate dielectrics other than SiO2 are now popular, models developed for SiO2 breakdown are used for these dielectrics too. Considering that the Si–O bond is very strong, modeling efforts have focused in ways to weaken it so that defect creation (bond-breaking) is commensurate with experimental observations. So far, bond-breaking models rely on defect-precursors to make the energetics manageable. Here, it is argued that the success of the percolation model for gate oxide breakdown precludes the role of defect precursors in gate oxide breakdown. It is proposed that defect creation involves "normal" Si–O bonds. This new model relies on the fact that hole transport in SiO2 is in the form of a small polaron—meaning that it creates a transient local distortion as it travels. It is this transient distortion that enables normal Si–O bonds to be weakened (albeit transiently) enough that breaking the bonds at a rate commensurate with measurements becomes possible without the help of the externally applied field. [ABSTRACT FROM AUTHOR]

The 1.7 kV 4H-SiC MOSFET which features optimized retrograded-profile ion implantation in the JFET regions (RG-MOS) is proposed and fabricated on the 4 inch wafers. The measured results quantify the benefits of the RG-MOS structure: simultaneous improvement in high-frequency figures of merit (HF-FOM) (R on× C GD) by 1.5×, HF-FOM (R on × Q GD) by 1.5× and Baliga figure of merit (BFOM = 4BV2/ R on,sp) by 1.6× compared with the conventional MOSFET (CON-MOS). Unlike other reported complicated structures which need high-precise fabricating process, the proposed RG-MOS structure is compatible with the prior planar 4H-SiC MOSFET process, and is favorable for large-scale production. [ABSTRACT FROM AUTHOR]

A germanium p-channel Schottky barrier metal–oxide–semiconductor field-effect transistor (SB-MOSFET) with germanium–platinum Schottky contacts is demonstrated experimentally. The fabrication process has a low thermal budget of 450 ° C and requires neither intentional doping nor ion implantation. At a temperature of 4 K, the p-channel SB-MOSFET turns on at a gate voltage of −1.6 V and shows a peak mobility of 500 cm2/V s at a carrier density of 3 × 1012 cm–2. Under high drain–source bias voltages, the device operates in an unconventional mode where the current is limited by the source contact. Injection of carriers from the source contact to the germanium channel is controlled by the gate bias, which modulates the Schottky barrier capacitively. The transconductance in this mode deviates from and is significantly higher than the value expected for a conventional MOSFET with the same geometry, mobility, and capacitance. Based on four-point current–voltage measurements, we present a theoretical band diagram of the device and give a physical picture for the observed high currents and transconductances. [ABSTRACT FROM AUTHOR]

The adverse effects of leakage currents and short channel effects (SCE) on mobility degradation in CMOS technology below the 100-nanometer scale. To mitigate these effects, the paper suggests using material engineering techniques to improve the mobility of charge carriers and control SCE effects. Specifically, the switching characteristics of a dual-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are enhanced by stacking the gate with various oxide layers including SiO2, HfO2, and TiO2. These oxide layers possess a range of permittivity capabilities from low to high. By combining different oxide layers the proposed device aims to improve its performance. To evaluate the performance of the proposed device we have employ simulation models such as CONMOB (Concentration Dependent Mobility), AUGER (Auger Recombination), and FLMOB (Field Dependent Mobility). These techniques help to obtain the accurate and reliable simulation results. We have utilized the parameters like drain current, transconductance, electric field, ION, IOFF, and ION/IOFF and simulate them using the Silvaco TCAD tool. The analysis of these parameters are discussed in the paper we have highlighted the compatibility of the proposed DGMOSFET device for low-power applications. In this paper, we have focus on the improving the switching characteristics of a dual-gate MOSFET by utilizing gate stacks with various oxide layers. The proposed device is evaluated through simulations using concentration-dependent mobility, Auger recombination, and field-dependent mobility techniques. The results indicate that the device is suitable for low-power applications. [ABSTRACT FROM AUTHOR]

For low-power circuit applications, the performance of the circuit is significantly influenced by the MOSFET's analog/RF and non-linearity properties. Gate-all-around junction-less accumulation mode MOSFETs (JAM) are now the perfect choice for low-power circuit applications. In the present work, the gate-stack engineering method is used for gate-all-around junction-less accumulation mode MOSFET (GSJAM) to improve the analog/RF characteristics. The analog/RF and linearity parameter analyses are numerically performed for a 20 nm channel length gate-all-around gate-stacked junction-less MOSFET using an ATLAS 3D device simulator. The comparative analysis of these analog/RF and linearity parameters is also done. The gate stack engineering shows significant improvements in analog/RF parameters, i.e., trans-conductance (gm), output resistance (Rout), early voltage (Vea), intrinsic gain (AV), trans-conductance frequency product (TFP), gain frequency product (GFP), trans-conductance generation factor (TGF), gain bandwidth product (GBWP), gain trans-conductance frequency product (GTFP), and cut-off frequency (fT). The results of the simulation investigation show that when GSJM is compared to JAM MOSFET, the values of gm, Rout, Vea, and TGF are all 26.37%, 2.24 times, 22.38%, and 20.78% higher, respectively. Also, the gate-stack junction-less MOSFET improves the linearity parameters, i.e., 2nd -order trans-conductance (gm2), 3rd -order trans-conductance (gm3), VIP2, VIP3, IIP3, IMD3, and 1-dBCP. When comparing GSJAM to JAM MOSFET, the values of VIP2 are 81.63% higher, VIP3 is 1.77 times higher, IIP3 is 6.72 times higher, and 1-dBCP is twice as high. Further, for analog/RF applications, a 20 nm CMOS common-source voltage amplifier circuit using gate-stake junction-less MOSFET has also been designed for a 20 mV and 1 GHz sinusoidal input signal. [ABSTRACT FROM AUTHOR]

This paper proposes a secondary‐side semi‐active series resonant converter with hybrid control. Compared with the traditional series resonant converter (SRC), the converter only replaces two diodes with metal oxide semiconductor field effect transistors (MOSFETs) on the secondary side of the transformer, without adding any auxiliary components. By employing hybrid modulation scheme, the proposed converter can achieve a wide output voltage range in a narrow switching frequency range with high efficiency and has excellent soft‐switching performance. Due to the large magnetizing inductor and narrow switching frequency range, the proposed converter can achieve energy delivery with high efficiency and high power density. This paper provides a detailed introduction to the working principle, circuit characteristics, and design process of the converter. Finally, a 3.3 kW SiC‐based experimental prototype with 400 V input, 250–430 V output, and a switching frequency of 120–140 kHz is built to verify the theoretical analysis, and the peak efficiency reaches 97.82%. [ABSTRACT FROM AUTHOR]

Summary: Metal oxide semiconductor field effect transistors (MOSFETs) are widely used in various power electronic systems, and the establishment of the electromagnetic compatibility (EMC) model for MOSFETs is crucial for EMC analysis of these systems, especially high‐frequency switching circuits. In this paper, a MOSFET EMC modeling method is proposed based on electrical characteristic measurement, simplex optimization, and particle swarm optimization (PSO), to make MOSFET models meet both functionality and EMC analysis requirements. First, systematic methods for extracting SPICE parameters based on physical MOSFETs are presented, including a proposed curve‐fitting method based on PSO for extracting the CDS‐VDS and ID‐VGS characteristic parameters. Second, parametric influence analyses are conducted on some important model parameters, and the law that these parameters affect the EMC of MOSFETs is obtained. Finally, the preliminary MOSFET model was optimized comprehensively using the simplex method. The measured and simulated results are in good agreement in both time domain and frequency domain. It proves that the established model meets the requirements for model accuracy in terms of both EMC and functionality. Therefore, the proposed EMC modeling method is feasible. [ABSTRACT FROM AUTHOR]

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the I – V characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes. [ABSTRACT FROM AUTHOR]

The imperative for continuous device miniaturization has heightened the need for logic reconfigurability due to its benefits in circuit design simplification and process optimization. Van der Waals ambipolar transistors, notable for their inherent reconfigurable characteristics, have garnered significant interest for their potential to revolutionize information electronics. Nevertheless, as the semiconductor thickness approaches the 3-nm mark, precise modulation of electrical polarity presents a considerable challenge as minor variations in thickness can lead to significant electrical disparities. Here, we introduce a silicon backend process-compatible approach by employing surface charge transfer doping to skillfully adjust the polarity in ambipolar transistors. This universal method can achieve a controllable p-type doping effect and good electrical symmetry in ambipolar semiconductors. Through careful calibration of the MoO3 dopant layer thickness, we significantly enhance the hole mobility in doped WSe2 field-effect transistors (FETs), increasing it from 8 to 100 cm2 V−1 s−1, surpassing the performance of most non-silicon p-type semiconductors. A thorough temperature-dependent doping characterization elucidates the deeper traps-induced Schottky barrier variation for hole transport, and a reduction in current fluctuation for electron transport in WSe2/MoO3 FETs. Leveraging the precision in electrical polarity control, we demonstrate a complementary logic inverter by integrating two doped ambipolar FETs on a single monolithic channel. This advancement paves the way for quasi-forksheet structures and underscores the benefits in evolving advanced processing technologies, steering toward scalable, cost-effective, and efficient electronic device fabrication. [ABSTRACT FROM AUTHOR]

Electrospinning has revolutionized the field of semiconductor metal oxide (SMO) gas sensors, which are pivotal for gas detection. SMOs are known for their high sensitivity, rapid responsiveness, and exceptional selectivity towards various types of gases. When synthesized via electrospinning, they gain unmatched advantages. These include high porosity, large specific surface areas, adjustable morphologies and compositions, and diverse structural designs, improving gas-sensing performance. This review explores the application of variously structured and composed SMOs prepared by electrospinning in gas sensors. It highlights strategies to augment gas-sensing performance, such as noble metal modification and doping with transition metals, rare earth elements, and metal cations, all contributing to heightened sensitivity and selectivity. We also look at the fabrication of composite SMOs with polymers or carbon nanofibers, which addresses the challenge of high operating temperatures. Furthermore, this review discusses the advantages of hierarchical and core-shell structures. The use of spinel and perovskite structures is also explored for their unique chemical compositions and crystal structure. These structures are useful for high sensitivity and selectivity towards specific gases. These methodologies emphasize the critical role of innovative material integration and structural design in achieving high-performance gas sensors, pointing toward future research directions in this rapidly evolving field. [ABSTRACT FROM AUTHOR]

Ambipolar electrolyte‐gated transistors (EGTs) based on reduced graphene oxide (rGO) have been demonstrated as ultra‐sensitive and highly specific immunosensors. However, the physics and chemistry ruling the device operation are still not fully unraveled. In this work, the aim is to elucidate the nature of the observed sensitivity of the device. Toward this aim, a physical–chemical model that, coupled with the experimental characterization of the rGO‐EGT, allows one to quantitatively correlate the biorecognition events at the gate electrode and the electronic properties of rGO‐EGT is proposed. The equilibrium of biorecognition occurring at the gate electrode is shown to determine the apparent charge neutrality point (CNP) of the rGO channel. The multiparametric analysis of the experimental transfer characteristics of rGO‐EGT reveals that the recognition events modulate the CNP voltage, the excess carrier density Δn, and the quantum capacitance of rGO. This analysis also explains why hole and electron carrier mobilities, interfacial capacitance, the curvature of the transfer curve, and the transconductances are insensitive to the target concentration. The understanding of the mechanisms underlying the transistor transduction of the biorecognition events is key for the interpretation of the response of the rGO‐EGT immunosensors and to guide the design of novel and more sensitive devices. [ABSTRACT FROM AUTHOR]

The field-effect transistor (FET) is a fundamental component of semiconductors and the electronic industry. High on-current and mobility with layer-dependent features are required for outstanding FET channel material. Two-dimensional materials are advantageous over bulk materials owing to their higher mobility, high ON/OFF ratio, low tunneling current, and leakage problems. Moreover, two-dimensional heterostructures provide a better way to tune electrical properties. In this work, the two distinct possibilities of PdSe2/MoSe2 heterostructure have been employed through mechanical exfoliation and analyzed their electrical response. These diffe approaches to heterostructure formation serve as crucial components of our investigation, allowing us to explore and evaluate the unique electronic properties arising from each design. This work demonstrates that the heterostructure possesses a better ON/OFF ratio of ∼5.78 × 105, essential in switching characteristics. Moreover, MoSe2 provides a defect-free interface to PdSe2, resulting in a higher ON current of ∼10 μ A and mobility of ∼63.7 cm2V−1s−1, necessary for transistor applications. In addition, comprehending the process of charge transfer occurring at the interface between transition metal dichalcogenides is fundamental for advancing next-generation technologies. This work provides insights into the interface formed between the PdSe2 and MoSe2 that can be harnessed in transistor applications. [ABSTRACT FROM AUTHOR]

A pulsed power supply with a short rise time and high repetition frequency is favorable to driving diffusive plasma for strongly oxidizing radical (O3, OH) generation and increasing the system's energy efficiency. In this paper, a 10-stage solid-state linear transformer driver (LTD) with a nanosecond rise time is developed to drive plasma for wastewater treatment. To decrease the rise time, a control system with low jitter is developed to improve the synchronization of pulses using an optocoupler isolation chip. A 10-stage LTD with a rise time of 6.2 ns is realized in the case that the rise time of the single-stage LTD is 5.4 ns. The results show that the LTD can generate pulses on a 300 Ω resistive load with a repetition frequency of 10 kHz, an amplitude of 8.80 kV, an overshoot less than 3.97%, and a reverse overshoot less than 4.82%. The rise time (6.2–33.0 ns), the pulse width (35.9–200.0 ns), and the fall time (10.5–27.6 ns) can be adjusted flexibly and independently by controlling the drive signals of metal oxide semiconductor field effect transistors. The pulsed generator is utilized to drive plasma in the needle-water electrode system. The preliminary experimental results show that the plasma includes abundant oxygen atoms and hydroxyl radicals with high activity, and it is suitable for wastewater treatment. [ABSTRACT FROM AUTHOR]

This paper presents a hardware implementation for the reliable design of a full silicon carbide (SiC) inverter-fed motor drive system. SiC MOSFETs have been widely used in various applications due to their low switching losses, high voltage capabilities, and high-temperature operation capability. However, SiC MOSFETs are vulnerable to the overvoltage and overcurrent caused by the high switching frequencies and faults of parasitic inductance. The high speed of switching transitions causes high dv/dt, which leads to insulation failures of motor windings. In addition, the high di/dt, according to the parasitic inductance, can destroy the switching devices under short-circuit faults. A gate driver with desaturation protection is required to prevent short-circuit faults, and a passive filter should be installed to reduce the dv/dt to within prescribed values. This paper presents an optimized design process for a full SiC inverter-fed motor drive system with improved reliability. The effectiveness and validity of the process are verified through experimental results under various conditions. [ABSTRACT FROM AUTHOR]

Summary: In this paper, introduces a DC–DC converter design based on a modified hybrid switched inductor‐switched capacitor architecture, aimed at achieving ultra‐high voltage gain in renewable energy systems (RES). The proposed converter involves adding a modified boosting conversion mode (MBM) that interleaves with the main switch to double the voltage transfer gain. Additionally, a modified switched capacitor (MSC) technique, utilizing two diodes as interleaved components, is integrated into the main and auxiliary switches to verify low voltage stress across them. In addition, modified hybrid switched inductors with capacitors (MSIC) and diodes are employed to validate ultra‐high voltage gain. The main advantages of the proposed converter are its high efficiency, low voltage stress across diodes and MOSFETs, and the utilization of low values of inductors and capacitors at high switching frequencies. In addition, the voltage stress across the inductors of the (MSIC) is reduced as the duty cycle increases. Furthermore, the current stress on the main switch is reduced when the charge of capacitor C1 becomes zero. Mathematical models for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) of the proposed converter are explored. Furthermore, a dual PI controller is designed for the proposed converter to maintain a high fixed output voltage. In addition, the PCB design and experimental testing of the proposed converter to verify the simulation and laboratory results. Specifically, the proposed converter is designed to boost up voltage (30–40 V) to a variable output voltage between 200 and 300 V at 300 W at efficiency 96.7%. [ABSTRACT FROM AUTHOR]

Due to the influence of parasitic internal parameters and junction capacitance, the silicon carbide (SiC) power devices are frequently marred by significant overshoots in current and voltage, as well as high-frequency oscillations during the switching process. These phenomena can severely compromise the reliability of SiC-based power electronic converters during operation. This study delves into the switching transient of the SiC MOSFET with the goal of establishing a quantitative correlation between the gate driving current and the overshoot in both the drain-source voltage and the drain current. In light of these findings, the innovative active gate drive (AGD) circuit, which features an adjustable gate current, is introduced. Throughout the switching process, the AGD circuit employs a dynamic monitoring and feedback mechanism that is responsive to the gate voltage and rate of change in the drain-source voltage and drain current of the SiC MOSFET. This adjustment enables gate driving current to be actively modified, thereby effectively mitigating the occurrence of overshoots and oscillations. To empirically validate the efficacy of the proposed AGD circuit in curbing voltage and current overshoots and oscillations, a double-pulse experimental setup was meticulously constructed and tested. [ABSTRACT FROM AUTHOR]

The burgeoning interest in non-classical MOSFET devices for low power applications and their latest incorporation in the newer technology node necessitate a study of Negative Capacitance Field Effect Transistors (NCFETs) in Radio Frequency applications. This work explores the comparative analysis of RF/analog performance of single gate NCFET (SG-NCFET) and highly doped double pocket double gate NCFET (HDDP-DG-NCFET) using performance parameters such as cut-off frequency (fT), transconductance frequency product (TFP) and transconductance generation factor (TGF). The Metal Ferroelectric Insulator Semiconductor based HDDP-DG-NCFET excels SG-NCFET in terms of enhanced performance in TGF and TFP. In addition, several important distortion parameters, such as intermodulation distortion and linearity, are also investigated for these devices. The behavior of distortion and linearity indices such as gm2, gm3 (higher-order transconductance), IIP3 (3rd order power-intercept point), higher order voltage intercept points (VIP2 and VIP3), 1 dB compression point, and total harmonic distortion is analyzed, which shows that HDDP-DG-NCFET exhibits distortion less performance. The influence of ferroelectric thicknesses and temperature on the RF/analog and linearity performance are also explored and described. The HDDP-DG-NCFET exhibits an ON current of 2.1 × 10−3 A/ μ m, current switching ratio of 0.79 × 1010, gm of 18.9 mS, fT of 2.65 THz, TFP of 64 THz/V, which is 55.56%, 111.27 times, 134.79%, 55.88%, 255.56%, respectively higher than SG-NCFET device. In addition, the subthreshold swing and OFF current of HDDP-DG-NCFET are 25.5 mV/decade and 2.65 × 10−13 A/ μ m, which is lesser than SG-NCFET. Moreover, it is witnessed that as the temperature rises from 250 to 400 K, RF/analog metrics are worsened while the linearity performance parameters are enhanced. Furthermore, it is observed that the proposed HDDP-DG-NCFET is linear compared to SG-NCFET with a lower magnitude of higher-order harmonics. Finally, these findings reveal that at lower voltages, HDDP-DG-NCFET outperforms SG-NCFET, evincing potential use of the same in RF applications. [ABSTRACT FROM AUTHOR]

A high-electron-mobility transistor (HEMT) structure consisting of a 15-nm-thick quaternary AlGaInN top barrier layer, a thin 200-nm-thick unintentionally doped (UID) GaN channel layer, and an AlN back barrier was grown on a single-crystal AlN substrate by metal–organic chemical vapor deposition. The HEMTs fabricated on the grown heterostructure exhibited DC pinch-off characteristics with no large negative resistance owing to the high thermal conductivity of the AlN substrate. The 2-μm-gate-length devices showed the maximum current density of 500 mA/mm and the peak transconductance of 120 mS/mm with the threshold voltage of approximately −4 V. The off-state leakage was less than 30 μA/mm thanks to the thin UID-GaN channel with good crystal quality. The pulsed I–V characteristics for the fabricated HEMTs showed much smaller drain current decreasing compared to the same structured HEMTs with a C-doped GaN back barrier on a SiC substrate. This indicates that the UID-GaN channel grown on the AlN substrate had no harmful impurity levels that cause the current collapse phenomenon. The above-mentioned results demonstrate that the combination of the thin UID-GaN channel and the AlN back barrier works effectively in GaN HEMTs, and it will contribute to the device design and fabrication for future high-power/high-frequency applications. [ABSTRACT FROM AUTHOR]

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler–Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration. [ABSTRACT FROM AUTHOR]

In this work, we report on the high-performance p-GaN/InGaN/AlN multi-heterostructure p-channel metal–semiconductor field effect transistors (MESFETs) with energy-band modulated quantum well-like InGaN channel and low work function metal tungsten (W) as the gate material. A negative threshold voltage (VTH) of −0.35 V is achieved by precisely controlling the self-aligned etching depth at the active region. Benefiting from the enhanced hole confinement, the ION/IOFF ratio and subthreshold swing of the fabricated-channel MESFET are extracted to be 1.2 × 107 and 66 mV/dec, respectively, at room temperature. The idealized Schottky interface with TMAH and post-gate-annealing treatment shows an ultra-low voltage hysteresis of 0.08 V extracted at subthreshold area in the dual-sweep transfer curves. [ABSTRACT FROM AUTHOR]

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal–oxide–semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model. [ABSTRACT FROM AUTHOR]

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown ( Q B D ) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the Q B D model of the device under test (DUT). Compared with the Q B D obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs. [ABSTRACT FROM AUTHOR]

The lack of suitable channel semiconductor materials has been a limiting factor in the development of tunneling field-effect transistor (TFET) architectures due to the stringent criteria of both air stability and excellent gate-tunable electronic properties. Here, we report the performance limits of sub-10-nm double-gated monolayer (ML) BiN TFETs by utilizing first-principles quantum-transport simulations. We find that ML BiN possesses an indirect bandgap of 0.8 eV and effective masses of 0.24m0 and 2.24m0 for electrons and holes, respectively. The n-type BiN TFETs exhibit better performance than the p-type ones, and the on-state current can well satisfy the requirements of the International Roadmap for Devices and Systems for both high-performance and low-power standards. Notably, we find that the BiN TFETs exhibit distinguished gate controllability with an ultra-low subthreshold swing below 60 mV/decade even with a small gate length of 6 nm, which is superior to the existing field-effect transistors, such as black phosphorus TFETs, GeSe TFETs, and BiN metal–oxide–semiconductor field-effect transistors. Furthermore, the BiN TFETs are endowed with the potential to realize high switching speed and low-power consumption applications because of their extremely short delay time and ultra-low power-delay product. Our results reveal that the ML BiN is a highly competitive channel material for the next-generation TFETs. [ABSTRACT FROM AUTHOR]

Diamond holds the highest figure‐of‐merits among all the known semiconductors for next‐generation electronic devices far beyond the performance of conventional semiconductor silicon. To realize diamond integrated circuits, both n‐ and p‐channel conductivity are required for the development of diamond complementary metal‐oxide‐semiconductor (CMOS) devices, as those established for semiconductor silicon. However, diamond CMOS has never been achieved due to the challenge in n‐type channel MOS field‐effect transistors (MOSFETs). Here, electronic‐grade phosphorus‐doped n‐type diamond epilayer with an atomically flat surface based on step‐flow nucleation mode is fabricated. Consequently, n‐channel diamond MOSFETs are demonstrated. The n‐type diamond MOSFETs exhibit a high field‐effect mobility around 150 cm2 V−1 s−1 at 573 K, which is the highest among all the n‐channel MOSFETs based on wide‐bandgap semiconductors. This work enables the development of energy‐efficient and high‐reliability CMOS integrated circuits for high‐power electronics, integrated spintronics, and extreme sensors under harsh environments. [ABSTRACT FROM AUTHOR]

In the current nanoscale regime, fin field effect transistor (FinFET) technology overcomes the limitations of metal oxide semiconductor field effect transistor (MOSFET) technology. Robust and low-power static random access memory (SRAM) design is a demanding task for memory designers, especially in the nanoscale regime. Therefore, this paper proposes a 10 transistor (10T)-based SRAM cell design using low-power FinFET technology. The proposed approach not only reduces the leakage current, but also improves cell stability in different states. The proposed SRAM cell is simulated and analyzed at a 10 nm technology node using a multi-gate predictive technology model (PTM) for the transistors with a power supply of 0.7 V. The comparison analysis is also presented with the existing designs. The read and write static noise margins, and SRAM electrical quantity matrix (SEQM) of the proposed SRAM cell are improved by 3.54×, 1.71× and 26.41×, respectively, compared with the conventional 6T (C6T) design. The reliability investigations and comparison of the proposed SRAM cell have been carried out using Monte Carlo simulations with ± 1 0 % deviations in the process parameters. The reliability analysis shows that the proposed SRAM cell is less sensitive to process variations. [ABSTRACT FROM AUTHOR]

The model of lateral β-Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) was established using Sentaurus Technology Computer Aided Design software. The gate-to-drain distance of the device was 13.7 μm, and the breakdown voltage was 1135 V. The single event effect simulation model caused by heavy ion irradiation was introduced, and the effects of heavy ions' incident position, angle, drain bias voltage, and linear energy transfer on the single event effect were studied. It is found that x = 7.7 μm is the sensitive location of the single event effect at the gate corner near the drain side and the peak value of the transient current is 177 mA/mm. The effect of the terminal structure of the field plate on the transient effect of the single event effect of β-Ga2O3 MOSFET is studied. It is also found that the sensitive position of the single event effect of the conventional structure, gate-field plate structure, and gate–source composite field plate structure is around x = 7.7 μm when VDS = 10 V. The peak transient currents obtained are 177, 161, and 148 mA/mm. The single event effect pulse current of the three structures increases with an increase in the drain bias voltage, while the peak pulse current of the conventional structure is larger than that of the gate-field plate structure and the gate–source composite structure. The research shows that the terminal structure of the field plate is reliable means to reduce the single particle effect. [ABSTRACT FROM AUTHOR]