Design and analysis of dual gate MOSFET with spacer engineering.

The adverse effects of leakage currents and short channel effects (SCE) on mobility degradation in CMOS technology below the 100-nanometer scale. To mitigate these effects, the paper suggests using material engineering techniques to improve the mobility of charge carriers and control SCE effects. Specifically, the switching characteristics of a dual-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are enhanced by stacking the gate with various oxide layers including SiO2, HfO2, and TiO2. These oxide layers possess a range of permittivity capabilities from low to high. By combining different oxide layers the proposed device aims to improve its performance. To evaluate the performance of the proposed device we have employ simulation models such as CONMOB (Concentration Dependent Mobility), AUGER (Auger Recombination), and FLMOB (Field Dependent Mobility). These techniques help to obtain the accurate and reliable simulation results. We have utilized the parameters like drain current, transconductance, electric field, ION, IOFF, and ION/IOFF and simulate them using the Silvaco TCAD tool. The analysis of these parameters are discussed in the paper we have highlighted the compatibility of the proposed DGMOSFET device for low-power applications. In this paper, we have focus on the improving the switching characteristics of a dual-gate MOSFET by utilizing gate stacks with various oxide layers. The proposed device is evaluated through simulations using concentration-dependent mobility, Auger recombination, and field-dependent mobility techniques. The results indicate that the device is suitable for low-power applications. [ABSTRACT FROM AUTHOR]