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Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral charge loss is reduced and, thus, long retention time are possible. In this work we present good memory action characterised by low write voltages, write times of the order of milliseconds and long retention time in spite of the low tunnel oxide thickness. © 2002 Elsevier Science B.V. All rights reserved.

Nitridation treatments are very important in CMOS technology because of their capability of improving the gate and tunnel oxide reliability. In this work we report on N2O and NO annealing of pre-oxidised samples showing physical and electrical characteristics of the thin oxides. The difference between the physical behaviours of N2O and NO oxides is evidenced and related to their different electrical properties.

We have studied the effects of nitridation with nitric oxide on the leakage current of thin (

The induced changes of the flatband voltage by the location of holes in a silicon-rich oxide (SRO) film sandwiched between two thin SiO 2 layers [used as gate dielectric in a metal-oxide-semiconductor (MOS) capacitor] can be used as the two states of a memory cell. The principle of operation is based on holes permanently trapped in the SRO layer and reversibly moved up and down, close to the metal and the semiconductor, in order to obtain the two logic states of the memory. The concept has been verified by suitable experiments on MOS structures. The device exhibits an excellent endurance behavior and, due to the low mobility of the holes at low field in the SRO layer, a much longer refresh time compared to conventional dynamic random access memory cells. © 2002 American Institute of Physics.

A simple and efficient model for first-order simulation of the writing of n-channel erasable programmable ROM (EPROM) cells is presented. It allows the current injected into the gate insulator of the cell transistor to be calculated, accounting (at first order) both for the nonMaxwellian form of the electron energy distribution and for the nonlocal nature of carrier heating. The model is implemented as a postprocessor of a two-dimensional device simulator, and it is validated by means of a comparison with experimental data obtained with devices with effective channel lengths ranging from 1.4 to 0.5 mu m. >

Double-gate and tri-gate FinFET type memories with nitride (SONOS-like) or Si nanocrystals storage with minimum feature sizes of 10 nm were realized. Strong performance advantages in program / erase characteristics and reliability deeply linked to the FinFET architecture are demonstrated.

FinFETs have been proposed for transistor scaling because of their improved robustness to short channel effects and excellent current drive. Recently, the finFET concept together with discrete trap storage has been studied for Flash memory scaling because of the advantage of reduced floating gate interferences and reduced cell-to-cel cross talk in high-density devices. We have realized Si nano-floating gate (NFM) finFET Flash devices with highly scaled active width and channel length. Improved performances and endurance compared with planar NFM devices are observed in 3D structures (fin width down to 20 nm). Localization of the inversion charge favors low aspect ratio finFET Flash devices with the additional advantage of improved manufacturability.

We have realized Si nanocrystal memory cells in which the Si dots have been deposited by CVD on SiO2 and then covered by a CVD control oxide. In this paper, we report a study on the potential of these cells for dual bit storage. © 2004 Elsevier B.V. All rights reserved.

The simulation of a realistic floating-gate EPROM (electrically programmable ROM) cell is carried out by the three-dimensional device simulator HFIELDS 3-D. The results obtained are in good agreement with measurements, because of the accurate description of both the device geometry and the impurity profile. The latter, in turn, is made possible by the adoption of a prism-based discretization scheme (which allows remarkable simplification of mesh and geometry management) and by extrapolating 2-D process simulation results. The critical amount of computations is faced by using iterative linear solvers which make it possible to keep CPU time reasonably low. Qualitatively relevant differences between 2-D- and 3-D-computed results are highlighted, related to the channel-width modulation due to the applied gate voltage. >

A novel EPROM (electrically programmable ROM) cell, suitable for production of very-high-density multimegabit memories, is described. The structure is a contactless crosspoint cell whose floating gate is self-aligned to word lines and bit lines. Strong reduction of cell area and contact number is achieved with respect to the conventional cell. Electrical characteristics and reliability behavior of this structure have been studied and are reported together with the fabrication process. It is noted that performances and scalability make this cell interesting for future multimegabit EPROM developments. >

Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage.

We investigate the memory function at room temperature in devices based on quantum dots. By Low Pressure Chemical Vapour Deposition (LPCVD) we deposited Si dots embedded in SiO2. On these devices flat band voltage shifts were well detected at low write voltages for write times of the order of milliseconds, and furthermore, a plateau in the flat band voltage shift, maybe consequence of Coulomb blockdale, was observed.

We have studied nanocrystal memory arrays with 2.56 × 105 cells (256kb) in which Si nanocrystals have been obtained by CVD deposition on a 4nm tunnel oxide. The cells in the array are programmed and erased by electron tunneling through the SiO2 dielectric. We find that the threshold voltage distribution has little spread. In addition the arrays are also very robust with respect to drain stress and show good retention.

To form crystalline Si dots embedded in SiO2, we have deposited thin films of silicon-rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH4 and O2. Then the materials have been annealed in N2 ambient at temperatures between 950°C and 1100°C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO2. The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory functions of such structures has been investigated in MOS capacitors with a SRO film sandwiched between two thin SiO2 layers as insulator and with an n+ polycrystalline silicon gate. The operations of write and storage are clearly detected by measurements of hysteresis in capacitance-voltage characteristics. A model which explains both the occurence of steady-state conduction through the SiO2/SRO/SiO2 stack at a relatively low voltage and the shift of flat-band voltage is presented and discussed. © 2001 Elsevier Science B.V. All rights reserved.

We have studied the effects of nitridation on the leakage current of thin (7-8 nm) gate or tunnel oxides. A polarity dependence of the tunneling current has been found this behavior is related to the presence of a thin silicon oxynitride layer at the SiO2/Si-substrate interface. The oxynitride layer lowers the tunneling current when electrons are injected from the interface where the oxynitride is located (substrate injection). The current flowing across the oxide when electrons are injected from the opposite interface (gate injection) is not influenced by the oxynitride. The increase of nitrogen concentration leads to a decrease of the tunneling current for substrate electron injection.

We suggest the possible contribution of multistep compound processes to light heavy-ion reactions at above-barrier energies. The presence of several correlation widths that characterize the fluctuation in energy of the excitation functions for different incident-outgoing channel combinations is indicated and demonstrated explicitly for the system /sup 12/C(/sup 15/N,..cap alpha..) at E/sub c.m./ = 9.51--17.33 MeV. The importance of multistep compound processes to heavy-ion fusion studies is pointed out.

Excitation functions and angular distributions of alpha particles emitted from the /sup 27/Al(/sup 3/He,..cap alpha..) and /sup 27/Al(p,..cap alpha..) reactions are measured at a composite nucleus excitation energy of about 30 MeV. The experimental results together with the widely varying correlation widths extracted from the fluctuation analysis are successfully interpreted on the basis of the statistical multistep compound emission mechanism. Confirmation is found of the interpretation of each experimental correlation width in terms of a coherent sum of the widths of the relevant stages of the reactions, previously proposed in the case of proton channels. Moreover, the ..cap alpha..-spectrum shape and the correlation width values are shown to be consistent with an ..cap alpha.. preformation picture of the target nuclei considered.

A number of (p,n), (n,p), and (/sup 3/He, p) reactions have been interpreted on the basis of the statistical multistep compound emission mechanism. Good agreement with experiment is found both in spectrum shape and in the value of the coherence widths.

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

By electrical measurements we investigate the charge trapping and the charge transport in MOS capacitors in which the gate oxide has been replaced with a silicon rich oxide (SRO) film sandwiched between two thin SiO2 layers.

This invention relates to a memory cell Which comprises a capacitor having a ?rst electrode and a second electrode separated by a dielectric layer. Such dielectric layer com prises a layer of a semi-insulating material Which is fully enveloped by an insulating material and in Which an electric charge is permanently present or trapped therein. Such electric charge accumulated close to the ?rst or to the second electrode, depending on the electric ?eld betWeen the electrodes,therebyde?ningdifferentlogiclevels.