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While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

International audience; In this paper, an innovative Schottky diode architecture is proposed and implemented in 130 nm BiCMOS technology. A state-of-the-art 1 THz cut-off frequency is measured and an innovative way to modify the height of the Schottky barrier is proposed. This smart way could enable zero-bias high-frequency circuit designs with a very low height value of the Schottky barrier in advanced BiCMOS technology without requiring any custom implantation.

In this paper, an innovative Schottky diode architecture is proposed and implemented in 55 nm BiCMOS technology. A State-of-the-art 1.7 THz cut-off frequency is measured and an analytical scalable model is proposed and experimentally validated paving the way for further performance improvement. In addition, this analytical model can be integrated in a Design Kit library in order to enable sub-THz Schottky diode-based circuit designs in advanced BiCMOS.

This paper deals with the optimization of a Si/SiGe HBT featuring an implanted collector and a DPSA-SEG emitter-base architecture. Arsenic and phosphorous doping species are studied. On the one hand, both silicon defects and dopants profiles control are evaluated and on the other hand, hf performances are presented. Carbon-phosphorous co-implantation is also investigated and a state-of-the-art 450 GHz $f_{\text{T}}$ HBT compatible with 55-nm MOSFETs is demonstrated through a device layout study.

This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.

RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has emerged over the past few years as the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology are already exceeding what was feasible using GaAs one, new cellular system such as carrier aggregation require even more stringent performances (linearity, power handling, insertion loss, isolation). To address those new requirements, RF SOI technology has to be improved. In this paper, the performances results of the latest generations of RF SOI switch technologies from STMicroelectronics are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also proposed, paving the way for RF SOI technology able to address 5G RF switches challenges.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 µm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz f T and 370 GHz f MAX associated with a CML ring oscillator gate delay τ D of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

10 GHz capacitance measurements are performed for the first time to reliably measure the inversion charge in downscaled devices. Effective mobility and average velocity are calculated. Obtained backscattering coefficients in both linear and saturation regimes clearly evidence the onset of non-stationnary transport but still far from the ballistic limit operation.

International audience; The influence of an additional annealing in the base/emitter module fabrication of state-of-the-art DPSA-SEG SiGe:C HBTs is studied in this paper. The objective of this annealing is to reduce the extrinsic base resistance R Bx which in previous studies appeared to limit f MAX of DPSA-SEG SiGe HBTs. TCAD simulations and on-silicon measurements are presented for two different base widths. It is shown that the f MAX increase brought by R BX reduction can be traded for a larger f T . A f T /f MAX frequencies couple reaching 320/390 GHz is demonstrated, associated to a CML ring oscillator gate delay time of 2.2 ps.

This paper summarizes the work carried out on the vertical profile of double-polysilicon SiGe:C HBTs to get f MAX above 400 GHz. The effects of the final spike annealing temperature, the emitter doping species, the base and collector doping levels and the Si capping layer thickness are presented and discussed.

We present in this paper the influence of the integration of the Selectively Implanted Collector (SIC) on the performance of +400 GHz fMAX Si/SiGe:C HBTs featuring a selective epitaxy of the base [1]. The process uses a standard collector module (n+ buried layer, collector epitaxy and collector sinker), a Bdoped Selective Epitaxial Growth of the SiGe:C base, and an As-doped emitter. An inside spacer module is employed to obtain emitter widths WE ~ 90 nm. The HBT front-end fabrication is finalized with a spike activation annealing, Co silicidation and contacts formation. The technology is based on a 130-nm CMOS core process with a thick copper back-end. As shown in Fig. 1, 2 different ways to integrate the SIC have been investigated. A first solution (Fig. 1a) is to implant the SIC right after the opening of the bipolar region, with a dedicated masking step. The advantage of this approach is to provide in addition ‘no-SIC’ transistors that offer larger Base-to-Collector (BVCBO) and Emitter-to-Collector (BVCEO) breakdown voltages. The drawback is that the SIC cannot be self-aligned to the EW and that its opening has then to be larger than the EW one in order to take into account the overlay tolerance. This may lead to an increase of the C – B capacitance CBC. Another solution (Fig. 1b) is to make it self-aligned onto the emitter window (EW), the implantation being done after the EW etching, through the pedestal oxide. . Table 1 presents electrical results for the 2 different SIC integration strategies cited above. 2 different collector doping levels (SIC − and SIC +) have been investigated for each. Implantations conditions have been adjusted to the SIC module to get comparable BVCBO values for SIC − (~6.0 V) and SIC + (~5.5 V). At first glance performances only depend on the SIC doping level and the well known fT / fMAX trade-off is observed. A large collector doping reduces the collector resistance RC and the C – B transit time τBC, which benefits to fT. On the opposite the CBC increases, which is detrimental to fMAX. State-of-the-art fMAX values > 400 GHz are obtained for all devices. A closer look at Table 1 shows on one side that although the CBC value depends on the collector doping level it depends more strongly on the SIC module, lower values being obtained with the ‘SIC after EW’ module. On the other side the base resistance RB*, determined from a dedicated test structure, is also significantly impacted by the choice of the SIC module. Indeed the extrinsic base resistance RBx increases with the ‘SIC after EW’ but the intrinsic base resistance RBi is unaltered. While the lower CBC values of the ‘SIC after EW’ module could be explained by SIC self-alignment, no simple reason could be found to explain the raising of the base resistance... TEM cross-sections have consequently been performed on devices coming from the 2 different SIC modules. The pictures from the SIC + transistors, presented in Fig. 2, show that in spite of an identical wet oxide etch recipe used for the cavity opening, the base cavity width depends strongly on the SIC integration choice! Although previous experiments did not show a clear correlation of the base resistance with the width of the link (LW) between the intrinsic base and the extrinsic (poly)base, we may estimate that a link as narrow as the one shown in Fig. 2 (right) could degrade RBx. Furthermore, a 16% increase of the unsilicided polybase sheet resistance has been noticed at parametric testing for the ‘SIC after EW’ module, which point to an insufficient resist thickness after EW etch to mask properly the As implantation from SIC. Arsenic dopants penetrate into the B-doped polybase increasing both the polybase sheet resistance and the extrinsic base resistance. They may also reach the pedestal oxide slowing down the oxide wet etch rate at the EW edges. Etch rate could also be impacted by the As implant in the EW. Process simulations will be performed to clarify these hypotheses that are supported by the fact that LW seems to depend on the SIC doping level. Fig. 3 shows that LW depends slightly on the EW width too. In conclusion, these results indicate that the ‘SIC before EW’ approach has probably more potential for improvements (by reducing the base cavity width) for next generation transistors requiring narrow EW and therefore thin resists.

This paper summarizes the work carried out to improve performances of a conventional double-polysilicon FSA-SEG SiGe:C HBT towards 400 GHz f MAX . The technological optimization strategy is discussed and electrical characteristics are presented. A record peak f MAX of 423 GHz (f T = 273 GHz) is demonstrated in SiGe:C HBT technology.

This paper presents the RF power performances of nLDMOSFETs fabricated on bulk and SOI substrates and the layout changes made to improve these performances. It is shown that simple design rules modifications can be done to increase f max , by reducing the gate resistance, without penalizing f T . A significant improvement of both the output power P out and the power added efficiency PAE is demonstrated in A and AB classes.

This paper presents a complete 0.13 mum SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2fF/mum2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors.

This paper presents the results of investigations on high-speed self-aligned Si/SiGe:C HBTs featuring a selective epitaxial growth of the collector. We detail the dc and ac characteristics of the devices and demonstrate the improvement of the control of doping profiles at the base/collector junction. State-of-the-art f T value of 350 GHz has been achieved, the f T BV CEO product being equal to 525 GHz. V.

THE suggestion that microanalysis of nitrogen, fluorine and uranium in fossil bones should be used for age determination1–4 assumes that the concentration of these elements varies uniformly in time. Vonach5 has plotted calibration curves for the N and F content of fossil bones from the past 108 yr. The nitrogen content, N, can be approximated by logN = −0.135 logt + 0.681 where N is weight per cent and t is age in years. The chemical changes that occur in buried bones depend on the composition of the surrounding minerals and the environmental conditions6. The concentration of a given element in bone is also influenced by biochemical differences between samples. Consequently, large fluctuations in N can be expected around the gross trend described by Vonach. We report here a fluctuation of the N content of bones that seems to correlate with climatic change.