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With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of multi-site testing efficiency owing to the limited number of tester I/Os and power capacity. In this paper, we present an advanced low pin count test architecture for efficient multi-site testing in semiconductors. To achieve this, the scan chain routing method is first exploited to reduce the power consumption during scan-based testing through a cluster-based approach, which is compatible with the test compression architecture. Subsequently, a new test compression architecture is proposed to encode test patterns and enable the testing of each device-under-test (DUT) through a low input test pin count by using the unique properties of the proposed tri-state detector and boundary scan architecture. The experimental results show the decrease in the test I/O requirements and test power consumption. Based on these improvements, the test application time (TAT) was significantly reduced for ISCAS’89 and IWLS’05 OpenCores benchmark circuits compared to the previous methods, without a heavy burden on the additional H/W area and routing overhead.

Many of the latent defects in modern day SoCs don't get activated at the time of final package tests carried out under Adaptive Voltage Scaling (AVS) and rated functional operating frequencies. As a result, chips with latent defects too pass the final package testing. The latent defects become active during initial period of operation in the field causing serious long term reliability issues. High voltage stress tests, when deployed methodically accelerate the chip ageing and are quite efficient in exposing latent defects that lead to early life failures or infant mortality. It helps in catching unreliable parts before they are shipped to the customers. For set-top box SoCs, Overvoltage stress test (OVST) is performed at 1.4x of nominal device operating voltage for a duration of 200ms to 400ms. The desirable toggle coverage for logic and memories is 85% or greater to expose majority of the potential latent defect sites. These parameters can vary for different product lines and are arrived at by carefully using a robust methodology touched upon in this paper. This paper demonstrates how a JTAG pins based low pin count scan test infrastructure can be leveraged to achieve 85% toggle coverage across the entire digital portion of the SoC. The OVST architecture ensures all the memories are active along with logic thus both are tested concurrently in a single test. This scheme eliminates separate logic and memory OVST tests culminating into less than one-fourth of original test-time and avoids excessive over stressing of the device.

The accurate measurement of temperature is vital across a broad spectrum of human activities. Temperature can be measured using temperature sensor. The temperature sensor and real-time clock are interfaced with microcontroller. Both the time and the temperature are displayed on LCD. The I2C protocol is used because of its numerous advantages such as low pin count, adaptability to the need of slave devices, and incorporation of ACK/NACK functionality to improve error handling. A simulation circuit is designed to read the values of temperature from −55 to 155 °C. The developed simplified economic hardware system measures the meteorological temperature with a reasonably good accuracy of ±1 °C. The temperature measurement with time is used in a wide range of applications such as industry, health care, science, and technology.

The latest accomplishments in the field of design and manufacturing of ICs enable entirely new application scenarios. For instance, the newest generation of electronic control units integrates a large number of sophisticated onboard ICs to implement advanced driver-assistance systems.

This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codewordbased compression scheme. Embedded test compression has proven to be beneficial and is widely used in industrial circuit designs. However, particularly, in test applications within lowpin-count environments, a certain number of test patterns is incompressible and will, therefore, be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy of safety-critical applications like automotive microcontrollers. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-theart techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4% and a test application time reduction up to 72.9% can be achieved when utilizing the existing multi-channel interfaces.

In this paper, the concept of active cell-balancing technique, by using a multiple-outputs double-forward converter for lithium-ion (Li-ion) batteries, is investigated. It controls two times more cells than secondaries, and it equalizes eight cells in a series. In this method, four secondaries can reasonably be wound with the same back electromotive force (EMF). This means a low pin count on the transformer and a low bill of materials (BOM). The bridge uses four N-channel MOSFETs as switches, which means two times fewer transistors than cells, resulting in fewer switching losses. This scheme is applied for controlling the minimum voltage among the cells of the lithium-ion battery. It uses a multi-winding transformer based on a forward double converter structure. Conventional schemes using a multi-winding transformer for electric vehicles (EVs) require an equal number of secondaries per cell. This scheme requires one secondary for two adjacent cells, thus the number of secondaries is reduced by a factor of two. Also, the redistribution of charge from a high cell to a low cell does not require many switching components and little intelligence to determine low cell voltage detection. The basic principle of this method is to use the overall battery pack voltage as a reference to supply individual cells, using a forward converter containing a transformer with a well-chosen winding ratio. The experimental and simulation results are performed to verify the feasibility of the proposed system.

Low pin count microcontrollers are used in numerous applications, especially in power control. Pin number reduction complicates real–time monitoring and debugging. Two modulation techniques for transmission data using PWM (Pulse Width Modulation) channel without significant influence on main application of this channel are proposed in this paper. Two modulation techniques: Additive Pulse Width Fluctuation and Differential Pulse Width Fluctuation are proposed with appropriate demodulation methods.

IC designs have been growing exponentially in size but the number of pins have not kept the same pace. This imbalance poses a difficult challenge when a design has very limited number of test pins but still requires a high quality testing. This problem is exacerbated when additional fault models like transition delay fault model are required for testing. This paper describes how a low pin count test controller was able to meet all these requirements to test a pin limited transceiver chip used in Qualcomm Technologies Inc.'s state-of-the-art chipset. The low pin count test controller supports at-speed testing with on-chip clock controller and exceeded the test coverage requirements for both stuck-at and at-speed testing by 1.22% and 2.16% respectively. During wafer testing, this test-pin savings enabled higher parallel testing of dies using multi-site testing which reduced the test-costs by about 1.6x.

Technology scaling made possible to increase IC capabilities from one node to the next by adding more transistors within the same die area while keeping a low pin count. As a consequence, test complexity increased exponentially, requiring engineers to use not only better test pattern generation software, but also powerful and expensive Automatic-Test-Equipments (ATE), usually not viable and accessible for small fabless start-ups and universities. In this work, we propose a low-cost and flexible ATE intended for manufacturing tests of the digital part of a multi-million gate industrial mixed signal ASIC produced in a 130nm technology that will be used at CERN in the ALICE experiment. The proposed ATE was built upon a ready-to-use platform including an embedded ARM-based processor and a FPGA to effectively apply the test vectors via the Device-Under-Test (DUT) scan chains in a feasible time and viable cost without the need for a PC. The ATE was operated to execute in-series manufacturing tests on two versions of the SAMPA chip, allowing identifying on-silicon defects.

Design-for-Testability (DFT) techniques for test cost reduction of digital circuits rely on efficient deployment of scan test through smart DUT (device under test) partitions, matching of scan test I/O needs to the DUT needs for increased scan data throughput, and optimal test pattern generation methods. The test cost is further reduced by testing multiple devices in parallel using the same set of ATE resources. As a result, the number of scan pins available in a DUT for test application is reduced. The need for managing different DUT partitions and ensuring that the scan I/O interface matches with the DUT requirements further aggravates the need for scan test pins. In this paper, a generic methodology for reduced pin count scan test is presented. Specific solutions are described for internal generation of all scan mode control signals, e.g. scan enable, clock control, X-mask control, switching between slow speed shift clock and high speed capture clock, etc., across one or more DUT partitions. It is shown how this method can ultimately lead to a single pin scan test solution. These methods have been implemented in cost sensitive SOC designs and, as a result, the scan test time has been reduced by 2x - 3x over what has been achieved using other aggressive test cost reduction methods for scan compression. These methods are also independent of the specific scan compression solution used.

Low speed IO signals on single ended lines such as the low pin count (LPC), high definition audio (HDA), serial peripheral interface (SPI) and so forth, typically has low emission energy from 30MHz onwards and normally meeting the EMC radiated emission requirements. However, the harmonics of these low speed IO signals may still pose the risk of interfering the RF bands such as the 3G/LTE/WCDMA and WiFi. These harmonics noise increases the noise floor of the platform at the mentioned RF bands and de-sensitizing the receive sensitivity. One of the root causes identified is the fast slew rate on the clock that causes the high amount of harmonics content. In this paper, an example of the data signal slew rate control on a flexible printed circuit (FPC) cable simulation model was being studied and with careful control of the data signal slew rate, the platform noise interfering with the GSM 850 bands can be reduced.

Test cost reduction is necessary to test a complex System-on-a-Chip(SoC) which adopts various Intellectual Properties (IP). In this paper, test architecture with low pin count which is able to IP-based SoC test, using IEEE Std. 1149.7 and IEEE Std. 1500, is proposed. IEEE Std. 1500 provides independent access mechanism for each IP in IP-based SoC test. In this paper, just two test pins are required by composing that these independent access mechanism can be controlled by IEEE Std. 1149.7. The number of Chips which are tested at the same time is increased by reducing required test pin count at wafer and package level test, and consequently the overall manufacturing test cost will be reduced significantly.

Recently, we must use the various scan test techniques for various purposes, for example, compression scan or LBST for mass-production test, LBIST for field test, legacy scan for fault diagnosis, and so on. Moreover, the number of the available external scan pins is different in each test process, for example, the parallel test process has a low pin count, the assembled chip test process has several pin counts depending on the assembled package types, and so on. Then, the cost-effective scan chain structure is also different for each purpose and each test process. In order to correspond to this situation, we introduce the multi-configuration scan structure which can change the numbers of scan chains. Evaluation result shows that our approach can improve test time for area overhead.

During the past two years copper wire bonding has entered high volume manufacturing at a number of leading edge OSATs and IDMs. Usage of copper wire has achieved 20% market share and is expected to exceed 50% within three years. Products spanning the range from low pin count devices with relatively large wire diameter to FPGA's with nearly one thousand wires at 20 μm or even 18 μm wire are now using copper wire. This paper will discuss the requirements for developing a robust copper wire bonding process and then moving it to high volume manufacturing. Process optimization begins with the selection of the appropriate wire diameter, ball diameter, bonding tool and bonding process type. These are functions not only of the bond pad opening, but also of the pad aluminum thickness and relative sensitivity of the pad to damage. Proper optimization depends on the availability of new and modified bond quality metrologies, such as extensive reliance on cross-sectioning and intermetallic coverage measurements. The bonding window of a copper wire bonding process is defined in substantially new terms compared to optimization in gold wire bonding. Once an optimized process has been developed in the lab on a single bonder, it needs to be verified. Copper wire bond processes are much less forgiving with respect to the acceptable variability on the manufacturing floor. To ensure that the process is stable, a low volume pre-manufacturing test is highly recommended. This not only makes sure that the process is stable across multiple bonders, but also ensures the adequacies of manufacturing controls, incoming materials quality and sufficient equipment calibration and maintenance procedures.

Copper wire bonding has huge cost advantages over gold wire bonding. As a result, low pin count, heavy wire applications have already been converted to copper wire and many companies are in high volume production. Recently, with the price of gold skyrocketing, conversion of high pin count (>250 I/O), high performance applications to Cu has dramatically accelerated. These high performance devices are increasingly relying on low-k materials under the bond pads. Unfortunately, the 33% greater hardness of Cu compared to gold places even greater stress on these inherently fragile materials. This can result in difficulties with pad damage and cratering of the underlying structures. Advancements have been made to copper wire bonders, tools, and wire that have resolved many of these issues and made fine pitch copper wire bonding feasible. Ni-based bond pads have emerged to solve the pad damage problem. Nickel is about 50% harder than copper and four times harder than aluminum so that it provides greater protection against the higher stress resulting from Cu ball bonding, as well as damage during probe. This is especially beneficial for devices with low-k active circuitry under the bond pad. NiPd, NiPdAu, and/or NiAu have demonstrated their great robustness to receive the Cu wire bonding with a huge wire bonding window without any splash and with excellent reliability.

This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM architecture to map SoC level failures to a particular embedded core. These TAM architectures allow high level of diagnosis resolution and performance.

A fully integrated multiparameter microsensor chip is presented for continuous monitoring of concentrations of different blood gases (e.g., pH, PO/sub 2/, pCO/sub 2/), ions, and biomolecules, and for conductometric measurements. The chip can monitor up to seven different chemical substances depending on the membranes deposited on the sensor units (on-chip ion-sensitive field-effect transistors (ISFETs), amperometric and conductometric cell). The sensors, which are positioned in a flow channel, are surrounded by on-chip interfacing and processing electronics so that external readout goes via a simple data acquisition card. In addition, temperature control of the measured fluids and a onetime-use security check have been provided for proper operation. Fabrication was done in a standard 1.2-/spl mu/m CMOS process to which extra postprocessing steps have been added for the chemical sensors and membranes. The chip operates at 5 V and the total die area is 25.7 mm/sup 2/. Full integration is obtained including the ISFETs and ISFET buffers, as well as a reference electrode structure, all integrated on the same chip in the same technology.

This paper outlines National Semiconductor's concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability.

Publisher Summary This chapter provides information on PIC microcontrollers and summarizes the additional features available in 8-bit PIC devices. The PIC 16F690 is selected for particular scrutiny, since it is used in Microchip's own basic demo hardware, the low pin count (LPC) board. The main groups of 8-bit (internal data) PIC flash devices are presented in a table and they are further divided into four groups: the 10F2xxx microcontrollers (MCUs) are the four input/output (I/O) devices with minimal features, the 12Fxxx series are eight-pin miniature PICs, the 16Fxxxx group is the mid-range series and the 18Fxxxx devices are the high-performance group with much larger memory and extensive I/O facilities. All PIC controllers use the same basic architecture and instruction set to provide a design progression path from simple programs to the most complex applications. The shared features of 8-bit devices include: Harvard architecture with RISC instruction set, flash program memory with in-circuit programming, RAM block including special function registers, and single working register and dedicated, non-writable stack among others.

Surface mount technology has revolutionized almost all aspects of end user product development. The commercial market in Japan has used low pin count surface mount packages for many years. Europe and the United States are rapidly expanding their own surface mount manufacturing expertise.

Advanced packaging conferences, technical articles, and editorials frequently focus on high pin count devices such as microprocessors and graphic processor devices. The substantial challenges incumbent on high I/O package designs warrant this attention. However, an entire universe of high performance packages with low pin counts also exist. Diodes, power transistors, RFIDs, engine controllers, and MEMs devices rarely demand more than eight terminals and often only require two. Almost all systems employ at least some low pin count devices. On the other hand, applications such as alternative energy equipment, LED lighting, automotive electronics, and ubiquitous sensor networks consist primarily of high performance, low pin count devices. In this paper the authors review families of applications that rely on high performance, low pin count devices and identify application-specific requirements such as power delivery, thermal management, signal integrity, and reliability. Next the paper analyzes the strengths and weaknesses of various packaging strategies, both traditional and emerging, developed for these applications. Specific package types considered include wire-bond, flip chip, hybrid, and embedded packaging as well as new approaches based on printed conductors, conductive adhesives, flexible substrates, and organic electronics. Finally, the authors assess the opportunities and challenges associated with packaging high performance, low pin count devices.

Copper wire bonding has huge cost advantages over gold wire bonding. Wire bonding and materials companies have invested heavily in R&D in the last 2 or 3 years and are starting to see the fruits of their labor. Low pin count, heavy wire packages have already been converted to copper wire and many companies are in high volume production. An extensive amount of development activity has targeted high pin count (>200 I/O) and high performance applications. Recently this work has paid off, as there has been an increase in this market segment that has drastically exceeded earlier predictions by market analysts. What the recent Research & Development has done is to actually fill in the knowledge gaps for copper wire bonding. This knowledge has fueled technology development, which, in turn, has enabled the current transition to high volume fine pitch production. In this paper I will discuss some of the technology developments that have overcome the challenges and make recommendations for implementing copper wire bonding as a replacement for gold in high volume manufacturing of high pin count packages. Specific areas of technology development that I will cover are advancements in stable free air ball formation, designs and techniques to eliminate or control pad damage, developments in molding compounds, and copper reliability fundamentals.

The VL86C010 processor, which is well suited to RISC applications because of its small die size, low power dissipation, and low pin count, is presented. This RISC processor family was designed for maximum system performance at minimum cost, rather than maximum CPU performance at any cost. The components of the system CPU, memory controller, IO controller, and video controller were partitioned to take advantage of less-expensive plastic IC packages and, more importantly, less-expensive dynamic RAM devices (DRAMs) by using their page mode of operation. These components are described, and the processor performance is examined. >

This paper explores some design factors, including wireability, of packages in which the number of I/O per module to be interconnected varies widely. This is of interest because it is common for memory card designs and for work station and personal computer printed circuit designs. Memory cards often have a few relatively high pin count control logic modules supporting many low pin count array modules. Work station and personal computer cards often use low density “glue” logic modules with a few microprocessor modules and their high function supports. Printed circuit cost and performance factors are examined by example. Differences between area array and perimeter escape components and leverage possibilities of multi-chip modules are examined. A background tutorial on wireability analysis is given. The algorithm used was developed by Wadie Mikhail several years ago. Analyses are based on the length of wire paths available in a given design, the length of wire needed and the utilizations of the available paths. Utilization guidelines are suggested. Alternative wireability algorithms are identified and briefly discussed. Although the examples are given for cases of modules on cards, the methodologies and general conclusions are valid at other packaging levels; for example, for chips on multi-chip modules.

We will show the real implementation of a very high test compression scheme for a 3 pin image sensor device. This new approach results in achieving the same compression ratio of 27.7X and the same test coverage on 3 pins instead of 8 pins for a typical scan design.

The dramatic price reduction of NAND Flash devices in recent years has created an opportunity for Flash to penetrate mass storage applications. This will happen provided the memory vendors can deliver NAND Flash devices with adequate performance and no intrinsic cost premium over the lowest cost conventional NAND Flash devices. The new HLNAND Flash Architecture facilitates this transition by enabling high performance NAND Flash devices with increased longevity and a cost advantage stemming from the low pin count interface and small die size.

In today's ICs low pin count is important to save space and reduce cost. The one-pin oscillator and the on-chip voltage multiplier are, among others, two analog circuits that help to accomplish this.

This chapter describes Trusted Computing Group (TCG) Main Specification modifications in regard to migration from a Trusted Platform Module (TPM) 1.1-based to a 1.2-based host system design. There are major modifications to the Main Specification and an introduction of totally new concepts, in addition to a completely new Low Pin Count (LPC)-based Trusted Interface Specification (TIS). The TIS adds a new concept concerning the physical and logical interface with regard to the LPC bus, and also introduces the concept of localities or entities that have different priority levels within the TPM device itself. Using the TIS interface, the TPM can distinguish between hardware, operating system, and application command requests. The most profound difference between the Version 1.1 and 1.2-based TPM realizations is found at the device driver layer, and concerns both the physical and the logical aspects based on the TPM LPC interface. It is noted that the Version 1.1-based commands augment and extend the Version 1.2-based Command Suite.

The capability of the Command Suite with regard to the Trusted Platform Module (TPM) is useless, without a means to communicate with the TPM. This can be achieved with the help of a well-defined Application Programming Interface (API). The Trusted Device Driver essentially gives the ability to communicate concerning the TPM physical interface and logically through a well-defined driver API. Atmel produces the only TPM with System Management Bus (SMBus) communication support. All the other flavors of TPM communicate via the Low Pin Count (LPC) interface. The LPC bus is a proprietary protocol that is generally associated with PC motherboard design. This chapter focuses on SMBus communication. The Trusted Device Driver Library (TDDL) contains the TCG-defined API, which allows any TCG Software Stack (TSS) secure stack to gain access to the TPM Command Suite via a well-defined and predictable software interface. The TDDL also contains information about how to communicate with specific vendor's TPM.

The goal of this paper is to present advantages of remote controlled 500W integrated electrical drive using infrared communication. A cost-effective, low pin count device for implementing IrDA standard wireless connectivity is used. Placing this device between Pocket PC (graphical user interface) and microcontroller (the heart of the speed motor system) is explained in details. Paper also shows performance and reliability of proposed communication showing advantages comparing to standard RS-232 interface

We report an innovative low cost leadless package concept with an ultra-miniaturized footprint and a significant height reduction. The package height has the potential to be made smaller than 0.4 mm. For discrete and low pin count solutions the package space can consume much less than 50% of present available standard packages. The package fulfills the typical first and second level reliability tests which include temperature cycling, pressure cooker or drop tests for low pin count solutions < 10 pins. We show results that the small and short contact pins lead to an excellent RF performance. The package is not only highly attractive for the discrete market, it also has remarkable potential for medium pin-count solutions. The package is capable for wireless and wireline solutions.

The P8xLPCxxx family of microcontrollers is designed for low pin count (LPC) applications with high functionality and a wide range of performance. There are two types of LPC devices—namely, P87LPC76x with EPROM/OTP code memory ranging from 1 KB to 4 KB, and P89LPC9xx with 4 KB to 8 KB of flash memory. All the LPC range incorporates 12C and UART serial interfaces and a Watchdog (Wd) timer. The P87LPC767, P87LPC768, and P87LPC769 devices all contain analog to digital converter (ADC) circuitry onboard. The P87LPC768 has pulse width modulation (PWM) while the P87LPC769 has digital to analog converter (DAC) circuitry onboard. The P89LPC932 has 8 KB of Flash code memory, 128 bytes of RAM data memory, and special features such as the capture/compare unit (CCU) and serial peripheral interface (SPI). The 87LPC769 is a 20-pin single-chip microcontroller designed for LPC applications. A member of the Philips LPC family, the 87LPC769 offers programmable oscillator configurations for high and low speed crystals or RC operation, wide operating voltage range, programmable port output configurations, selectable Schmitt trigger inputs, LED drive outputs, and a built-in watchdog timer. The P89LPC932 device is based on a high-performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC932 to reduce component count, board space, and system cost.

With increased demand for small form factor packages at low cost, wafer level packaging has emerged as the package of choice for many devices. Wafer level packages can be examined by package construction: redistribution/bump, copper post/bump with epoxy resin, encapsulated bond, and encapsulated beam lead. Production examples of each type of package construction in volume production are detailed. The paper addresses the drivers for wafer level packaging - today and in the future. Discussed is the proliferation of wafer level packages for low pin count devices and barriers for expansion including wafer level testing.

The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is typically used without underfill, solder joint reliability is of prime concern. A good understanding of the device failure mechanism when assembled on different board configurations is critical to the development of an accurate predictive model of solder fatigue. This paper presents results of a joint effort to develop a parametric predictive model of the solder joint reliability of the micro-SMD subjected to thermo-mechanical stresses. An 18 I/O micro-SMD was used as the primary test vehicle for the thermal cycling and thermal shock tests performed with different ramp/hold profiles. The parametric model developed can be extended to different pin count and die size of WL-CSPs with eutectic solder.

There are two competing technologies pursuing the 'holy grail' of complete system integration. Today, the most common method used to create the 'system' is to mount separately packaged ICs on a next-level substrate. Even with a low pin count, a package is typically several times larger than the IC, to accommodate the low wiring density on the PCB. High-performance systems, such as network processor systems, require high data bandwidth between key components and thus need an increased number of signal I/Os. Wide I/O busses switching at high speeds consequently require a larger number of power and ground pins to reduce switching noise. As a result, system performance is limited by increasing package size and the associated parasitic inductance and capacitance of the package and its connection on the PCB. System on chip (SoC) architecture attempts to integrate many functions, both analog and digital into a monolithic device. The successes are many, but so are the challenges. Many functions cannot be optimized due to the limitation of the semiconductor substrate used. Also, as defect density scales with area, the notion of integrating large scale functions (memory, switch fabrics) with small scale functions (rf devices) results in compounded yield impacts. System in Package (SiP) technology allows heterogeneous devices to be integrated into a small form factor. The integration technology includes embedded devices in the substrate and 3 dimensional chip-stacking approaches. By using a silicon based SiP, a copper/low K interconnect defined by lithographic processes on silicon offers very dense routing with high speed, low noise signal paths. The ICs used in the SiP can be designed to leverage the high density interconnect by optimizing both the core and the I/O of each device. Additionally, specialized devices can be designed specifically for the SiP architecture to take advantage of the high bandwidth and low latency features. Reducing chip-to-chip bus capacitance can dramatically decrease system power requirements and thermal dissipation. The lower bus power can be traded against higher bus frequency to improve performance at a fixed power level.

A low cost CMOS process controller for power amplifiers (PAs) in TDMA standards is presented. It fits into a 3/spl times/3 mm/sup 2/ package for minimum PCB area. Low pin count imposes digital control by switching on the supply and monitoring steps of some millivolts. It prevents PA damage for high VSWR and uses ESD protection accepting negative voltages in an n-well process.

The converter consists of a third-order sigma-delta modulator, comb and finite impulse response (FIR) filters, a digital noise shaper, and a sixth-order switched-capacitor filter. The converter operates on a single +5-V supply and uses serial I/O to maintain a low pin count. The serial interface allows up to four devices to be connected, thus providing four channels of coherently sampled A/D and D/A I/O. High-level software modeling was used to simulate the system signal-to-noise performance, thereby providing design goal verification. >

This paper describes the implementation of a test method that automates the pin by pin measurement of conducted RF emissions at the I/O lines of automotive electronic modules. Previous approaches required the test technician to place the RF probe on each I/O pin for each measurement individually. For low pin count modules, this is not a problem. For a module with an I/O pin count between 100-200 pins, the traditional procedure can be time consuming and physically tiring on the test personnel. Additionally, the technician will be moving the probe and its cable for each measurement, introducing an orientation variance with each measurement. These two facets of the measurement can lead to measurement repeatability issues. The automated method described herein reduces test time by 400%, and increases repeatability substantially.

Product miniaturization is driving the industry to introduce smaller form factor products-typically, chip-scale or chip-size packages (CSPs). Applications include consumer products such as digital camcorders and cameras; mobile phones and other handheld communications products; IC and memory cards; and portable computers. In addition, CSPs are finding their way into products where increased density is critical. CSPs offer many of the advantages of bare die-tested die, size, weight, and low profile-but at the same time provide a packaged solution. Low pin count devices are increasingly being packaged in CSPs, with larger volumes shipping every year. More than 100 CSP varieties have been introduced and many versions are shipping in high volume. This stimulates questions as to which packages are in high volume use for each application; which applications use the ultimate CSP, the wafer level packages; what the drivers are for these packages in each application area; what products will be seen in the future; and how packages will change to meet the needs of these products. This paper addresses these questions by examining the trends in CSPs and the high volume applications driving the explosion of growth in this emerging area.

The continued emphasis on higher-density (smaller) and better-performance (faster) on electronics system design makes the board (PCB layout) design become more complex and usually will challenge the DFM guidelines currently applied by the industry. For example, the design of mirrored BGAs on double-sided board, which is not recommended by current industry DFM guidelines, due to the real estate constraint. In fact, there are several successful design applying low pin count mirrored or staggered BGAs or CSPs for certain applications, such as memory modules.

Publisher Summary Together, disk operating system (DOS) and the read-only memory basic I/O system (ROM BIOS) perform all of the operating system functions necessary to support the personal computer (PC), such as managing directories and files, displaying text and graphics, and loading and executing programs. They also perform tasks that one might not be aware of, such as determining the type of equipment installed in a PC or formatting a hard disk. The ROM BIOS houses all of the low-level routines for controlling I/O operations. The DOS routines, on the other hand, operate at a higher level than the ROM BIOS routines. Some of the DOS routines make calls to the ROM BIOS. Thus, if one is concerned about the performance of a program that one is writing, one should use the ROM BIOS directly. QuickC provides a complete set of built-in functions for accessing both DOS and the ROM BIOS. The chapter presents most of the major functions that are available. These functions are divided up into three main categories: general DOS interrupt calls, BIOS interrupt calls, and general interrupt calls which allow to access either DOS or the ROM BIOS.