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Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated traps (GTs), and their relative contributions are studied. The time exponents of ${\Delta }\text{V}_{\mathrm{ T}}$ and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with ${t} _{T}{}_{iN}$ . When ${t} _{\mathrm{ TiN}}$ is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both ${\Delta }\text{V}_{\mathrm{ HT}}$ and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an ${f}$ -dependent process and that its relative contribution to ${\Delta }\text{V}_{\mathrm{ T}}$ increases with ${t} _{\mathrm{ TiN}}$ , which is an important factor for the improvement of NBTI through ${t} _{\mathrm{ TiN}}$ scaling. more...

In this letter, we present an experimental study on the frequency ( f ) dependence of trap generation under AC negative bias temperature instability (NBTI) stress in Si p-channel fin field-effect transistors (p-FinFETs), by adopting the direct-current current voltage (DCIV) method and an energy profiling technique. The interface trap generation ( $\Delta ~\text{N}_{IT}$ ) and bulk trap generation ( $\Delta ~\text{N}_{OT}$ ) are separated from the measured DCIV data and their ${f}$ dependences are independently investigated. The DCIV results indicate that the observed strong ${f}$ dependence of trap generation is primarily attributed to the ${f}$ -dependent $\Delta ~\text{N}_{OT}$ that exhibits a 36% reduction when ${f}$ increases from 10 Hz to 1 MHz. Furthermore, this ${f}$ -dependent $\Delta ~\text{N}_{OT}$ is mainly distributed between ${\text{E}_{v}}$ and ${\text{E}_{i}}$ , and exhibits a visible ${f}$ -dependent peak of energy density around ${\text{E}_{c}}$ . more...

The impact of the field reduction effect on negative bias temperature instability (NBTI) parameter characterization and lifetime prediction was quantitatively studied in p-MOSFETs with a sub-1 nm equivalent oxide thickness (EOT). By comparing NBTI results under constant field stress and constant voltage stress, the field reduction effect was found to become severer at higher VG-STR and ${T}$ and cause a reduction in the voltage acceleration factor (VAF) at higher VG-STR and a reduction in activation energy EA at higher ${T}$ under constant voltage stress. To accurately evaluate NBTI lifetime, a modified NBTI model with field reduction correction (FRC) was proposed, and the 10-year NBTI degradation of a 32-stage ring oscillator was simulated. The results showed that the conventional model without including FRC had a worse prediction capability and overestimated frequency degradation for a ring oscillator. It is necessary to use an NBTI model with FRC for NBTI lifetime prediction of devices with a sub-1 nm EOT. more...

In this paper, degradation behaviors of short channel high-klmetal gate p-FinFETs under hot carrier stress (HCS) and constant voltage stress (CVS) were compared to clarify the coupling ratio of NBTI component in hot carrier degradation (HCD). A discharge-based multi-pulse (DMP) technique was carried out to accurately analyze the energy distribution of interface trap and bulk trap under different stress conditions. Experiments show that the threshold voltage shift under CVS is about 3 times larger than that under HCS with the same stress bias. For both HCD and NBTI, the bulk hole trapping is dominant. more...

In this letter, the effect of TiN capping layer on interface quality and the channel hot carrier (CHC) reliability of high-k/metal-gate (HKMG) nMOSFET was investigated. Experiments show that the fresh interface trap density was reduced from ${1.83}\times {10}^{{11}}$ to ${7.75}\times {10}^{{10}}$ cm−2 for 1.4 and 2.4 nm ALD TiN capping layers, respectively, while the CHC time-to-failure was worsened by 13%. Combining the chemical analysis by secondary ion mass spectroscopy and the characterization of active energy for trap generation, it is found that the extraordinary chlorine introduced by a ALD TiN capping layer deposition could be responsible for the improved fresh interfacial trap but degraded CHC reliability in HKMG nMOSFETs. The mechanism can be explained by the lower binding energy of Si–Cl than Si–H, which results in more interface passivation but easier to be broken by electrical stress. This finding can provide the guide for the optimization of HKMG process. more...

A comprehensive study of the negative and positive bias temperature instability (NBTI/PBTI) of 3D FinFET devices with different small channel lengths is presented. It is found while with the channel lengths shrinking from 100 nm to 30 nm, both the NBTI characteristics of p-FinFET and PBTI characteristics of n-FinFET turn better. Moreover, the channel length dependence on NBTI is more serious than that on PBTI. Through the analysis of the physical mechanism of BTI and the simulation of 3-D stress in the FinFET device, a physical mechanism of the channel length dependence on NBTI/PBTI is proposed. Both extra fluorine passivation in the corner of bulk oxide and stronger channel stress in p-FinFETs with shorter channel length causes less NBTI issue, while the extra nitrogen passivation in the corner of bulk oxide induces less PBTI degradation as the channel length decreasing for n-FinFETs. The mechanism well matches the experimental result and provides one helpful guide for the improvement of reliability issues in the advanced FinFET process. more...

We use fast characterization methods to study DC and AC negative bias temperature instability (NBTI) kinetics in pMOSFETs with varying TiN capping layer thickness (tTiN). The effects of tTiN scaling on the threshold voltage shift (ΔV t ), pre-existing hole traps, and generated traps (ΔN t ) and their relative contribution are characterized. The time exponents of ΔV t and ΔN t and the effects of stress bias, temperature, frequency, and duty cycle on the degradation are analyzed. Devices with lower tTiN show reduced DC and AC NBTI, and a lifetime improvement of 60% is realized when tTiN is scaled down from 3 to 1 nm. We experimentally confirm that bulk trap generation (ΔN ot ) is an f-dependent subcomponent and that its relative contribution in ΔV t reduces with lower tTiN, which is the main reason for the improvement in NBTI through tTiN scaling. more...

Fast characterization methods are used to study negative bias temperature instability (NBTI) kinetics in replacement metal gate Si p-FinFETs filled by atomic layer deposition (ALD) tungsten (W) using B2H6 or SiH4 precursors. The impact of ALD W filling metal process on threshold voltage shift (ΔVT), generated interface traps (ΔNIT), pre-existing hole traps (ΔNHT), stress bias, and temperature dependence of degradation is analyzed. SiH4-based devices show lower ΔVT compared to B2H6-based devices under identical stress conditions due to lower ΔNHT and ΔNIT. More fluoride-passivated interface traps and higher compressive strain along the channel for ALD W using SiH4 are utilized to explain a lower ΔNIT than ALD W using B2H6. The time kinetics of NBTI degradation is then modeled for long-term prediction and the maximum overdrive voltage is determined. Devices filled with ALD W using SiH4 show superior reliability and a higher operation overdrive voltage, and can be adopted in the 16/14-nm node CMOS technology and beyond. more...

A comparative study on negative bias temperature instability (NBTI) is carried out in replacement metal gate Si p-FinFETs featuring atomic layer deposition (ALD) tungsten (W) filling metal using B2H6 and SiH4 precursors. A fast measurement technique is used to characterize the threshold voltage shift (ΔVT). The effect of ALD W filling metal process on ΔVT, generated interface traps (ΔNIT), pre-existing hole traps (ΔNHT), stress voltage, and temperature dependence of degradation is demonstrated. Comparing with their B2H6-based counterpart, SiH4-based devices show reduced ΔVT under identical stress conditions due to reduced ΔNHT and ΔNIT. SiH4-based devices exhibit a 1.5 times higher fluorine content at the interfaces and larger compressive strain in the channel than B2H6-based devices, which are found to be responsible for the reduced ΔNIT. A modeling framework is proposed to model the long-term time evolution of NBTI degradation, and the predicted maximum overdrive voltage is compared. SiH4-based devices exhibit superior reliability and a 20% improvement in the maximum operation overdrive voltage than B2H6-based devices, and can be implemented in the advanced CMOS technology. more...

In this study, ultra-fast methods were used to measure the threshold voltage shift $(\Delta\mathrm{V}_{\mathrm{T}})$ of the negative bias temperature instability (NBTI) in p-channel complementary metal oxide semiconductor field effect transistors (p-CMOSFETs) with a high-klmetal gate (HK/MG) stack. The voltage (Vg,str) and temperature (T) dependence of the NBTI time exponent (n) were studied under a wide range of stress conditions, and the results demonstrated a strong T dependence of n above room temperature (RT) and that the field reduction effect played an important role in determining the dependence of $n$ on Vg,str and T. With the direct current current-voltage (DCIV) method, the similarity of n, activation energy (EA) and voltage acceleration factor $(\Gamma)$ between the trap generation $(\Delta \mathrm{N}_{\mathrm{T}})$ and $\Delta \mathrm{V}_{\mathrm{T}}$ indicates that $\Delta \mathrm{N}_{\mathrm{T}}$ is the dominant subcomponent at higher values of T. The impact of the field reduction effect on the time exponents of $\Delta\mathrm{V}_{\mathrm{T}}$ and $\Delta\mathrm{V}_{\mathrm{T}}$ , EA, and $\Gamma$ were also investigated. more...