A Comparative Study of TiN Thickness Scaling Impact on DC and AC NBTI Kinetics in Replacement Metal Gate pMOSFETs

We use fast characterization methods to study DC and AC negative bias temperature instability (NBTI) kinetics in pMOSFETs with varying TiN capping layer thickness (tTiN). The effects of tTiN scaling on the threshold voltage shift (ΔV t ), pre-existing hole traps, and generated traps (ΔN t ) and their relative contribution are characterized. The time exponents of ΔV t and ΔN t and the effects of stress bias, temperature, frequency, and duty cycle on the degradation are analyzed. Devices with lower tTiN show reduced DC and AC NBTI, and a lifetime improvement of 60% is realized when tTiN is scaled down from 3 to 1 nm. We experimentally confirm that bulk trap generation (ΔN ot ) is an f-dependent subcomponent and that its relative contribution in ΔV t reduces with lower tTiN, which is the main reason for the improvement in NBTI through tTiN scaling.