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In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned bodies (UTBs). In other words, the operation of the MCFET theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET a gate length of 50 nm are extracted and discussed. Thanks enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (AVI) and early voltage (VEA) are superior compared with that single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (CGG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both CGG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications. [ABSTRACT FROM AUTHOR]

Abstract: For the first time, the high frequency (HF) performance of an ultra-thinned body (UTB) fully depleted silicon-on-insulator (FDSOI) incorporating TiN/HfO2 gate stack is reported. Full small signal equivalent parameters of UTB-FDSOI are extracted and analysed in detailed. It is revealed that UTB-FDSOI with longer unit width WU (same total width WTOT ) results in slightly higher gm that leads to better HF performance. Despite of the mobility degradation due to the quality of the interface between the high-K dielectric and silicon, the measured transition frequency (fT ) still corresponds well to that predicted from the ITRS roadmap. Optimising the gate stack for low RG is crucial as huge RG in the current technology is the key parameter responsible for the low fMAX obtained. This work can also be considered as the first ever experimental device measured suitable to be used for the Low STand-by Power (LSTP)-based RF/mobile application. [Copyright &y& Elsevier]

Abstract: This work presents a systematic analysis on the impact of source–drain engineering using gate “non-overlapped” on the RF performance of nano-scaled fully depleted Double Gate SOI transistors, when used in the design of a typical two stage Operational Transconductance Amplifier (OTA). It is evident that for a gate length less than 40nm, the incorporation of optimal source–drain engineering requiring a spacer length, which may exceed the length of the gate, is particularly beneficial in analogue applications. Lengthening the spacer reduces gate capacitance in the weak/moderate inversion region more than transconductance, improving cut-off frequency f T. This improvement is particularly significant in a circuit application where an optimal spacer of 1.5 times the gate length is proposed. This gate under-lapped concept with extended spacer can also significantly enhance DC gain of the OTA, by increasing the Early Voltage, while maximising the transconductance to current ratio in the weak to moderate inversion, close to threshold voltage. With optimally designed devices, the sensitivity of OTA circuit performance to doping profile is shown to be relatively low. [Copyright &y& Elsevier]

Abstract: In this paper, the analogue performance of a 65nm node double gate SOI (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f T, and f MAX. It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7nm/decade. Analytical expressions, which reflect the dependence of f T, and f MAX on extrinsic source, drain and gate resistances R S, R D and R G have been derived. While R D and R S have equal effect on f T, R D appears to be more influential than R S in reducing f MAX. The sensitivity of f MAX to R S and R D. has been shown to be greater than to R G. [Copyright &y& Elsevier]

Abstract: Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L g reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of the gate delay and on–off current ratio to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulations. The impact of the spacer length and doping gradient to the device and circuit performance are comprehensively investigated. It was found that the HP and LOP DGSOI could achieve the ITRS specification with a wider range of parameter combinations than the LSTP. [Copyright &y& Elsevier]

In this paper, measured RF noise performance of graded-channel metal-oxide-semiconductor (MOS) transistors (GCMOS--also named laterally asymmetric channel transistors) shows impressive reduction in minimum noise figure (N Fmin) as compared to classical MOSFET transistors (with the same gate length Lg = 0.5 μm). The reason is proven to be because of the higher noise correlation coefficient (C). GCMOS also shows lower sensitivity to extrinsic thermal noise as compared to classical MOSFET. Moreover, it is demonstrated that the use of 0.5-μm-gate-length GCMOS gives a competitive RF noise performance as compared to 0.25-μm-gate-length classical nMOS transistors. [ABSTRACT FROM AUTHOR]

This paper presents a detailed RF study for source/drain Schottky-barrier (SB) MOSFETs. Using on-wafer S-parameters, high-frequency (HF) figures-of-merit (FoMs) and small-signal equivalent circuits (SSEC) are first extracted and discussed for a 120-nm-gate-length SB MOSFET. Then, using ac simulations, HF FoM's sensitivity along SB height and underlap length variations are subsequently presented. The whole study provides, for SB MOSFETs, a deep understanding of key ac-element (transconductances and capacitances) behavior as well as process-parameter optimization to achieve the best HF FoMs. [ABSTRACT FROM AUTHOR]