Analog/RF Performance of Multichannel SOI MOSFET.

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned bodies (UTBs). In other words, the operation of the MCFET theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET a gate length of 50 nm are extracted and discussed. Thanks enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (AVI) and early voltage (VEA) are superior compared with that single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (CGG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both CGG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications. [ABSTRACT FROM AUTHOR]