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Electrical operation of room-temperature (RT) single dopant atom quantum dot (QD) transistors, based on phosphorous atoms isolated within nanoscale SiO2 tunnel barriers, is presented. In contrast to single dopant transistors in silicon, where the QD potential well is shallow and device operation limited to cryogenic temperature, here, a deep (∼2 eV) potential well allows electron confinement at RT. Our transistors use ∼10 nm size scale Si/SiO2/Si point-contact tunnel junctions, defined by scanning probe lithography and geometric oxidation. “Coulomb diamond” charge stability plots are measured at 290 K, with QD addition energy ∼0.3 eV. Theoretical simulation gives a QD size of similar order to the phosphorous atom separation ∼2 nm. Extraction of energy states predicts an anharmonic QD potential, fitted using a Morse oscillator-like potential. The results extend single-atom transistor operation to RT, enable tunneling spectroscopy of impurity atoms in insulators, and allow the energy landscape for P atoms in SiO2 to be determined.

Building low-power and high-density circuits requires new devices, which can be based for example on single electron effects. Single electron transistors (SET), which can operate at room temperature (RT), are candidates with high potential for the post-CMOS era. However, their fabrication relies typically on a statistical fabrication of quantum dots or positioning of nanoparticles or molecules between predefined electrodes. These methods hamper a scaled-up fabrication of RT-SETs. Here, we present a route for reproducible fabrication of RT-SETs on the basis of field-emission scanning probe lithography (FE-SPL) and cryogenic reactive ion etching. Due to the unique capabilities of our FE-SPL tool, enabling pre- and post-inspection of features, highly reliable patterning and precise feature alignment are obtained. The fabricated devices exhibit single electron effects at RT. A combination of this method with nanoimprint lithography would enable a high throughput and reproducible way of RT-SET fabrication.

Following a brief historical summary of the way in which electron beam lithography developed out of the scanning electron microscope, three state-of-the-art charged-particle beam nanopatterning technologies are considered. All three have been the subject of a recently completed European Union Project entitled "Single Nanometre Manufacturing: Beyond CMOS". Scanning helium ion beam lithography has the advantages of virtually zero proximity effect, nanoscale patterning capability and high sensitivity in combination with a novel fullerene resist based on the sub-nanometre C60 molecule. The shot noise-limited minimum linewidth achieved to date is 6 nm. The second technology, focused electron induced processing (FEBIP), uses a nozzle-dispensed precursor gas either to etch or to deposit patterns on the nanometre scale without the need for resist. The process has potential for high throughput enhancement using multiple electron beams and a system employing up to 196 beams is under development based on a commercial SEM platform. Among its potential applications is the manufacture of templates for nanoimprint lithography, NIL. This is also a target application for the third and final charged particle technology, viz. field emission electron scanning probe lithography, FE-eSPL. This has been developed out of scanning tunneling microscopy using lower-energy electrons (tens of electronvolts rather than the tens of kiloelectronvolts of the other techniques). It has the considerable advantage of being employed without the need for a vacuum system, in ambient air and is capable of sub-10 nm patterning using either developable resists or a self-developing mode applicable for many polymeric resists, which is preferred. Like FEBIP it is potentially capable of massive parallelization for applications requiring high throughput., ImPhys/Charged Particle Optics

Cost-effective generation of single-digit nano-lithographic features could be the way by which novel nanoelectronic devices, as single electron transistors combined with sophisticated CMOS integrated circuits, can be obtained. The capabilities of Field-Emission Scanning Probe Lithography (FE-SPL) and reactive ion etching (RIE) at cryogenic temperature open up a route to overcome the fundamental size limitations in nanofabrication. FE-SPL employs Fowler-Nordheim electron emission from the tip of a scanning probe in ambient conditions. The energy of the emitted electrons (<100 eV) is close to the lithographically relevant chemical excitations of the resist, thus strongly reducing proximity effects. The use of active, i.e. self-sensing and self-actuated, cantilevers as probes for FE-SPL leads to several promising performance benefits. These include: (1) Closed-loop lithography including pre-imaging, overlay alignment, exposure, and post-imaging for feature inspection; (2) Sub-5-nm lithographic resolution with sub-nm line edge roughness; (3) High overlay alignment accuracy; (4) Relatively low costs of ownership, since no vacuum is needed, and ease-of-use. Thus, FE-SPL is a promising tool for rapid nanoscale prototyping and fabrication of high resolution nanoimprint lithography templates. To demonstrate its capabilities we applied FE-SPL and RIE to fabricate single electron transistors (SET) targeted to operate at room temperature. Electrical characterization of these SET confirmed that the smallest functional structures had a diameter of only 1.8 nanometers. Devices at single digit nano-dimensions contain only a few dopant atoms and thus, these might be used to store and process quantum information by employing the states of individual atoms., European Union (European Union); Horizon 2020; European Research Council (ERC) European Union's Seventh Framework Program; FP7/2007-2013

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.