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Organic lead halide perovskite solar cells (PSCs) have become a viable alternative for next‐generation photovoltaic systems. The significance of reproducibly processing perovskite with less defects comes from the fact that imperfections have a major impact on the solar cell's performance and long‐term stability. Although it is well known that cautious precursor processing has a significant influence on perovskite defect generation, there haven't been extensive investigations on the serial associations between precursor processing, perovskite orientation, and defect generation in PSCs. Making use of a unique precursor chemistry treatment technique that facilitates uniaxially oriented perovskite growth, it is aimed to mitigate defects of sequentially spin‐coated perovskite. Through the temperature‐dependent configurational entropic effect on coordination between iodoplumbate and dimethylsulfoxide (DMSO), a DMSO de‐intercalation processing method is developed. This method enables the induction of uniaxially‐oriented α‐FA0.9MA0.1PbI3‐xBrx (FA: formamidnium, MA: methylammomnium, x < 0.13) perovskite growth parallel to substrates. As a result, this processing delivered significant advances in power conversion efficiency (24.02%) and ambient operational stability under light. This straightforward technique provides a accesible process for producing efficient and stable perovskite solar cells, enabling uniaxially oriented perovskite fabrication without complicated procedures or additional substances. [ABSTRACT FROM AUTHOR]

Quasi‐2D Ruddlesden–Popper perovskite (RPP) have surfaced as a promising candidate for light emitting diodes (LEDs) due to its outstanding optoelectronic properties. However, a reliable approach for patterning RPPs remains elusive due to the use of polar solvents in lithographic processes, which can damage the RPP. Here, a reliable and damage‐free dry micropatterning method of RPPs is reported, which also offers a cost/time advantage compared to conventional patterning methods. The sharp edges of high aspect ratio silicon micropillars are used to cut RPPs to a pre‐defined shape and then the cut RPPs are delaminated to obtain a patterned array of RPPs. The resultant patterned array exhibits no sign of degradation or discernable difference between adjacent pixels, achieving a ≈100% yield. The obtained array is utilized to fabricate a pixelated LED where a sharp electroluminescence (EL) spectrum peaking at 410 nm with full‐width‐at‐half‐maximum (FWHM) of 10 nm is observed. The pixelated devices demonstrate the potential to suppress EQE drops as the pixel size decreases, attributed to both the damage‐free micropatterning process and the defect tolerance of RPPs. Moreover, further improvements of the patterning method are demonstrated to avoid parasitic emission and suggest a promising strategy to fabricate pixel‐accessible micro‐LEDs. [ABSTRACT FROM AUTHOR]

Graphene epitaxy on the Si face of a SiC wafer offers monolayer graphene with unique crystal orientation at the wafer-scale. However, due to carrier scattering near vicinal steps and excess bilayer stripes, the size of electrically uniform domains is limited to the width of the terraces extending up to a few microns. Nevertheless, the origin of carrier scattering at the SiC vicinal steps has not been clarified so far. A layer-resolved graphene transfer (LRGT) technique enables exfoliation of the epitaxial graphene formed on SiC wafers and transfer to flat Si wafers, which prepares crystallographically single-crystalline monolayer graphene. Because the LRGT flattens the deformed graphene at the terrace edges and permits an access to the graphene formed at the side wall of vicinal steps, components that affect the mobility of graphene formed near the vicinal steps of SiC could be individually investigated. Here, we reveal that the graphene formed at the side walls of step edges is pristine, and scattering near the steps is mainly attributed by the deformation of graphene at step edges of vicinalized SiC while partially from stripes of bilayer graphene. This study suggests that the two-step LRGT can prepare electrically single-domain graphene at the wafer-scale by removing the major possible sources of electrical degradation.

The fundamental parameters of majority and minority charge carriers--including their type, density and mobility--govern the performance of semiconductor devices yet can be difficult to measure. Although the Hall measurement technique is currently the standard for extracting the properties of majority carriers, those of minority carriers have typically only been accessible through the application of separate techniques. Here we demonstrate an extension to the classic Hall measurement--a carrier-resolved photo-Hall technique--that enables us to simultaneously obtain the mobility and concentration of both majority and minority carriers, as well as the recombination lifetime, diffusion length and recombination coefficient. This is enabled by advances in a.c.-field Hall measurement using a rotating parallel dipole line system and an equation, [DELTA][mu].sub.H = d([sigma].sup.2H)/d[sigma], which relates the hole-electron Hall mobility difference ([DELTA][mu].sub.H), the conductivity ([sigma]) and the Hall coefficient (H). We apply this technique to various solar absorbers--including high-performance lead-iodide-based perovskites--and demonstrate simultaneous access to majority and minority carrier parameters and map the results against varying light intensities. This information, which is buried within the photo-Hall measurement.sup.1,2, had remained inaccessible since the original discovery of the Hall effect in 1879.sup.3. The simultaneous measurement of majority and minority carriers should have broad applications, including in photovoltaics and other optoelectronic devices. A carrier-resolved photo-Hall technique is developed to extract properties of both majority and minority carriers simultaneously and determine the critical parameters of semiconductor materials under light illumination., Author(s): Oki Gunawan [sup.1] , Seong Ryul Pae [sup.2] , Douglas M. Bishop [sup.1] , Yudistira Virgus [sup.1] , Jun Hong Noh [sup.3] [sup.4] , Nam Joong Jeon [sup.3] , [...]

A photoelectrochemical (PEC) water splitting device based on a dual‐junction monolithic tandem cell that utilizes NiOOH/FeOOH/BiVO4/SnO2/Ta:SnO2 (TTO)/tunnel oxide passivated contact (TOPCon) Si is reported. The PEC device achieves a maximum photocurrent density of 1.4 mA cm−2 (equal to a solar‐to‐hydrogen conversion efficiency of 1.72%) in 1.0 m potassium borate solution (pH 9) when illuminated with air mass 1.5 G simulated solar irradiation, which is the highest value among dual‐junction monolithic photoelectrochemical cells except for III–V materials. The TOPCon Si not only works as an appropriate bottom photoelectrode for subsequent high‐temperature BiVO4 processing but also offers a high photovoltage of 590 mV. Transparent and conductive TTO grown by pulsed laser deposition serves as a recombination layer to achieve effective integration. In addition, the TTO provides chemical and physical protection, allowing the surface of the TOPCon Si to exhibit 24 h of tandem cell stability under weak base electrolyte conditions. The SnO2 hole‐blocking layer inserted between TTO and BiVO4 enhances the charge separation of BiVO4, allowing the device to achieve high efficiency. Artificial leaf‐type monolithic tandem cells consisting of NiFe/BiVO4/SnO2/TTO/TOPCon Si/Ag/Ti/Pt with a solar‐to‐hydrogen efficiency of 0.44% are also demonstrated. [ABSTRACT FROM AUTHOR]

The power‐conversion efficiencies of orthorhombic tin selenide (α‐SnSe)‐based thin‐film solar cells (TFSCs) are very low—less than 1% in most cases—due to the poor crystallinity, small grains, and large number of defects. Herein, the highest cell efficiency of 2.51% together with a high short‐circuit current density of 28.07 mA cm−2 for α‐SnSe TFSCs grown via vapor‐transport‐deposition (VTD) is reported. The grain size and surface roughness of the SnSe thin films greatly influence the shunt properties of the device. Significantly large shunt losses are detected in the case of both small and extremely large grains. The shunt losses for SnSe thin film with small grains are associated with high grain‐boundary scattering. The presence of extremely large grains results in high surface roughness of the SnSe thin film, which causes nonuniform deposition of the CdS buffer layer and, consequently, higher shunt losses. The SnSe thin film with moderate‐sized grains and inferior surface roughness exhibits improved shunt properties owing to uniform deposition of the CdS buffer layer and subsequent layers and thereby significant improvement in the device performance. The potential of orthorhombic VTD‐SnSe thin films as an emerging cost‐effective absorber layer for TFSCs is experimentally demonstrated. [ABSTRACT FROM AUTHOR]