46 results on '"Le Gratiet, B."'
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2. The image lab sandbox, pulling image computing in wafer fab metrology environment.
3. Analysis and modelling of patterned wafer nano-topography using multiple linear regression on design GDS and silicon PWG data.
4. New approach for APC and measurement sampler interaction in a complex process mix logic fab.
5. Contour based metrology, getting more from a SEM image.
6. Investigating process variability at ppm level using advanced massive eBeam CD metrology and contour analysis.
7. Advanced in-production hotspot prediction and monitoring with micro-topography
8. Advanced in-production hotspot prediction and monitoring with micro-topography
9. CHAM: weak signals detection through a new multivariate algorithm for process control
10. An evaluation of edge roll off on 28nm FDSOI (fully depleted silicon on insulator) product
11. Verification and application of multi-source focus quantification
12. Process window optimizer for pattern based defect prediction on 28nm metal layer
13. Analysis and modelling of patterned wafer nano-topography using multiple linear regression on design GDS and silicon PWG data
14. New approach for APC and measurement sampler interaction in a complex process mix logic fab
15. Contour based metrology: getting more from a SEM image
16. Investigating process variability at ppm level using advanced massive eBeam CD metrology and contour analysis
17. AGILE integration into APC for high mix logic fab
18. Product layout induced topography effects on intrafield levelling
19. Scatterometry-based metrology for the 14nm node double patterning lithography
20. Predictability and impact of product layout induced topology on across-field focus control
21. How holistic process control translates into high mix logic fab APC?
22. 14nm FDSOI technology for high speed and energy efficient applications
23. 28nm FDSOI high-K metal gate CD variability investigation
24. In-field in-design metrology target integration for advanced CD and overlay process control via Dosemapper and high order overlay correction for 28nm and beyond logic node
25. 28nm FD-SOI metal gate profile optimization, CD and undercut monitoring using scatterometry measurement
26. Advanced in-production hotspot prediction and monitoring with micro-topography
27. A solution for an ideal planar multi-gates process for ultimate CMOS?
28. Aging study in advanced photomasks: impact of EFM effects on lithographic performance with MoSi binary and 6% attenuated PSM masks
29. Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications
30. First CMOS integration of ultra thin body and BOX (UTB2) structures on bulk direct silicon bonded (DSB) wafer with multi-surface orientations
31. Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
32. Effect of Poly/SiON Gate Stack Combined with Thin BOX and Ground Plane for Low Vth and Analog Applications of FDSOI Devices
33. CHAM: weak signals detection through a new multivariate algorithm for process control
34. Process window optimizer for pattern based defect prediction on 28nm metal layer
35. An evaluation of edge roll off on 28nm FDSOI (fully depleted silicon on insulator) product
36. Verification and application of multi-source focus quantification
37. Fine-pattern lithography for large substrates using a holographic mask-aligner
38. Pt and Pt/Cu carbonyl clusters synthesized by radiolysis
39. Product layout induced topography effects on intrafield levelling
40. AGILE integration into APC for high mix logic fab
41. Predictability and impact of product layout induced topology on across-field focus control
42. How holistic process control translates into high mix logic fab APC?
43. 28nm FD-SOI metal gate profile optimization, CD and undercut monitoring using scatterometry measurement
44. Scatterometry-based metrology for the 14nm node double patterning lithography
45. 28nm FDSOI high-K metal gate CD variability investigation
46. In-field in-design metrology target integration for advanced CD and overlay process control via DoseMapper and high order overlay correction for 28nm and beyond logic node
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