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Increased space system performance is enabled by access to high-performance, low-power radiation-hardened microelectronic components. While high performance can be achieved using commercial CMOS foundries, it is necessary to mitigate radiation effects. This paper describes approaches to fabricating radiation-hardened components at commercial CMOS foundries by the application of novel design techniques at the transistor level, the cell level, and at the system level. This approach is referred to as hardness-by-design. In addition, trends in the intrinsic radiation hardness of commercial CMOS processes will be discussed. Index Terms--Hardness-by-design (HBD), multibit upsets, single-event latchup, single-event transient, single-event upset, total-ionizing dose radiation.

Radiation-induced edge-leakage current in minimum geometry n-channel MOSFETs from five submicron technologies is examined as a function of dose rate. Under worst-case bias, degradation of transistors from the TSMC 0.35-, 0.25-, and 0.18-[micro]m processes is more severe following low-dose-rate irradiation than following high-dose-rate irradiation and anneal. The leakage current anneals with an activation energy of ~1.0 eV, which suggests that charge trapping in the field oxide is associated with shallow defects such as [E'.sub.[delta]] centers. A comparison of the device response to a first-order kinetics model for hole trapping and annealing indicates that the enhanced degradation results from slower annealing rates following low-dose-rate irradiation. These results suggest that space charge in the field oxide may contribute to the dose rate sensitivity by altering the spatial distribution of trapped holes. In contrast to the response of the TSMC parts, high-dose-rate irradiation and anneal hounds low-dose-rate degradation of transistors from the HP 0.50- and 0.35-[micro]m processes. These results imply that existing qualification approaches based on high-dose-rate irradiation and anneal may not be conservative for the hardness assurance testing of some advanced CMOS devices. Index Terms--Anneal, dose rate, [E'.sub.[delta]] center, edge-leakage current, field oxide, hardness assurance, ionizing radiation, MIL-STD-883F Method 1019.6, metal-oxide-semiconductor field-effect transistor (MOSFET), space charge.

The use of annular MOSFET design, which has demonstrated total-dose radiation immunity in CMOS circuits, n improve the hot-carrier reliability of CMOS circuits by reducing the drain electric field compared to conventionally designed MOSFETs. A theoretical analysis of the annular n-MOSFET in saturation verifies the reduction of the drain electric field in properly designed MOSFETs. Hot-carrier data for an enclosed 0.25-[micro]m n-MOSFET demonstrate an improvement in hot-carrier lifetime by more than 3x compared to a conventional device in the same technology. Index Terms--Annular MOSFET, edgeless MOSFET, enclosed VIOSFET, hot-carrier, reliability.

Results are presented on technique using displacement damage from energetic ions to suppress single event latchup in commercial off-the-shelf (COTS) CMOS integrated circuits. Ions implanted through the back of a thinned chip degrade the parasitic bipolar transistors causing latchup without degrading chip functionality or the parametrics of the chip. Index Terms--COTS CMOS integrated circuits, displacement damage to suppress latchup, single event latchup suppression.

We report the thresholds for laser-induced latchup on epicaxial CMOS test structures for 600 nm and 815 nm excitation. We analyze the differences observed in terms of different iatchup triggering mechanisms and compare the results with measurements of energetic particle-induced latchup. Index Terms--Latchup, single event effects, picosecond, laser, epicaxial, cmos.

The geometric component of charge pumping current was examined in n-channel metal-oxide-silicon field effect transistors (MOSFETs) following low-temperature irradiation. In addition to the usual dependencies on channel length and gate bias transition time, the geometric component was found to increase with radiation-induced oxide-trapped charge density and decreasing temperature. A postirradiation injection of electrons into the gate oxide reduces the geometric component along with the density of oxide-trapped charge, which clearly demonstrates that the two are correlated. A fit of the injection data to a first-order model for trapping kinetics indicates that the electron trapping occurs predominantly at a single type of Coulomb-attractive trap site. The geometric component results primarily from the bulk recombination of channel electrons that fail to transport to the source or drain during the transition from inversion to accumulation. The radiation response of these transistors suggests that Coulomb scattering by oxide-trapped charge increases the bulk recombination at low temperatures by impeding electron transport. These results imply that the geometric component must be properly accounted for when charge pumping irradiated n-channel MOSFETs at low temperatures. Index Terms--Bulk recombination, capture cross-section, charge pumping, Coulomb scattering, geometric component, hot electrons, interface trap density, irradiation, low-temperature, mobility degradation, MOSFET, oxide-trapped charge, trapping kinetics.

An improved separation technique is presented for metal-oxide-silicon (MOS) capacitors, which accounts for the deactivation of substrate dopants by hydrogen at elevated irradiation temperatures or small irradiation biases. The technique is demonstrated on a p-type MOS capacitor irradiated with (sup 60)C gamma rays at 100 degree C and zero bias with significant dopant deactivation.

Radiation-hard ASIC design is enabled by the trend in commercial microelectronics toward increased radiation hardness, demonstrated here with new radiation results on a 0.25-[micro]m commercial process utilizing shallow trench isolation. A design comparison is made between creating ASICs targeting a traditional rad-hard foundry, which may be more than two generations behind commercial foundries, applying hardness-by-design methodology at a commercial foundry, and directly targeting a commercial foundry using commercial design practices.

Metal-oxide-silicon capacitors fabricated in a bipolar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate accepters following high-dose-rate irradiation at 100 [degrees] C. Accepter neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of [H.sup.+] ions in the oxide and Si layers and the availability of holes in the Si depletion region. The capacitor data were used to simulate the impact of accepter neutralization on the current gain of an irradiated npn bipolar transistor. Neutralized accepters near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that accepter neutralization may complicate hardness assurance test methods for linear circuits, which are based on elevated temperature irradiations.