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The cache memory system for CalmRISC32 embedded processor is described in this paper. A dual data cache system structure called a cooperative cache that takes advantage of design flexibilities of a dual cache structure is used as the cache memory system for CalmRISC32 to improve performance and reduce power consumption. The cooperative cache system is applied to both data cache and instruction cache. This paper describes the structure and operational model of the cache memory system for CalmRISC32. The implementation of the cache memory system for CalmRISC32 is also presented.

A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor, the prototype chip of which was recently manufactured with a 0.25 /spl mu/m, 4-metal process by Samsung Electronics Co.