Search

A procedure is proposed for obtaining identification (ID) numbers using polycrystalline silicon (poly-Si) thin-film transistors (TFT).

The effect of a gate-all-around thin-film transistor (GAT) with a lightly doped drain structure on the reduction of the off-current is studied. The off-current of the GAT is found to be almost the same as that of a single-gate TFT with an LDD structure although the GAT's channel area is about twice as big as that of the SGT. The suppression mechanism of the individual performance variations in the GAT is also investigated by thinning the channel poly-Si.

An asymmetric memory cell, a single-bit-line static random access memory cell, was designed using a complementary thin-film transistor (C-TFT). The structure of the C-TFT was constructed with n-channel and p-channel TFTs which share the same gate. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4 micrometer design rules. The cell was found to be capable of stable read and write operations with further decreases cell size.

A study was conducted to characterize a unique static random access memory cell called complementary-switch cell. The cell, which integrates a single-bit-line architecture, features a C-switch that combines a bn-channel bulk transistor and a p-channel TFT. It also supports low-voltage operation for read and write operation and is capable of minimizing cell size more effectively than standard cells.

A novel approach of assessing threshold voltage shift variation due to negative-bias temperature stress in poly-crystalline silicon thin-film transistors (Si tft) has been devised. The technique centers around poly-silicon boundary and poly-Si/SiO2 interface negative-bias temperature stress. Evidence from the chemical reaction indicates that two types of hydrogenated dangling bonds exist. The technique is applicable to poly-crystalline Si tft device development.

Dynamic random access memory cells using a vertical phi-shape transistor (V-Phi-T) cell effectively process information of 1 Gbit and above. The V-Phi-T cell is an efficient vertical MOSFET with a 4F(super 2) size, where F is the minimum feature size. The V-Phi-T cell forms by the penetration of a gate electrode followed by the formation of a channel plug within the penetrating hole. The electrical properties of the cell improve with scaling down.