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Li–oxygen batteries could provide energy density that is up to five times greater than that of state-of-the-art Li-ion batteries. However, Li–oxygen cell rechargeability is limited by cathode passivation due to nonconductive discharge products. Despite efforts to efficiently oxidize these products, oxygen recovery remains poor at potentials where cell constituents are stable. Transition metal oxide (TMO) cathodes have shown low charging potentials, but a correspondence to improved oxygen evolution efficiency is debated. This is because the deposition of electrically insulating Li2O2 during the battery discharge could passivate the TMO surfaces and render them inactive for catalyzing oxygen evolution during charge. Contrary to this, we show that TMOs enable charging at low overpotentials without compromising the oxygen evolution efficiency. Charge potentials are lowered by 130–400 mV in batteries employing TMO-based cathodes compared to carbon-only cathodes. By a combination of current-sensing atomic force...

Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first review recent advances in the application of NVM devices to three computing paradigms: spiking neural networks (SNNs), deep neural networks (DNNs), and ‘Memcomputing’. In SNNs, NVM synaptic connections are updated by a local learning rule such as spike-timing-dependent-plasticity, a computational approach directly inspired by biology. For DNNs, NVM arrays can represent matrices of synaptic weights, implementing the matrix–vector multiplication needed for algorithms such as backpropagation in an analog yet massively-parallel fashion. This approach could provide significant improvements in power and speed compared to GPU-based DNN training, for applications of commercial significance. We then survey recent research in which different types of NVM devices – including phase change memory, conductive-bridging RAM, filamentary and non-filamentary RRAM, and other NVMs – have been proposed, either as a synapse or as a neuron, for use within a neuromorphic computing application. The relevant virtues and limitations of these devices are assessed, in terms of properties such as conductance dynamic range, (non)linearity and (a)symmetry of conductance response, retention, endurance, required switching power, and device variability.

Large-scale 3D crossbar arrays can enable both high-density Storage Class Memory (SCM) and novel non-Von Neumann computation. Such arrays require each nonvolatile memory (NVM) element to have its own non-linear Access Device (AD), to pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Typically, power consumption during write, not read margin, is the most stringent constraint for large $1{\rm AD}+1{\rm R}$ crossbar arrays. We extend our circuit-level SPICE simulations—previously performed just for large arrays of an AD based on Cu-containing Mixed-Ionic-Electronic-Conduction (MIEC)-materials together with a generic NVM element $(+1{\rm R})$ —to three additional diode-like ADs as well as three threshold-switching ADs. We show that the suitability of an AD for 1AD1R memories is strongly dependent upon both nonvolatile memory (NVM) and circuit parameters, as well as the AD's own intrinsic properties. We find that building large arrays $(\geq 1~{\rm Mb})$ with $\geq 10~\mu{\rm A}$ NVM current is only possible for MIEC ADs and moderate NVM switching voltage $(\leq 1.2~{\rm V})$ . None of the ADs studied here support larger NVM switching voltage $(\geq 1.2~{\rm V})$ unless switching current is $\leq 10~\mu{\rm A}$ . The effects of line resistance, low-current (10–100 pA) bias condition, stacking two ADs vertically, and reductions in TVS threshold current are all studied. The particular AD parameters that would need to be improved to affect each AD's prospects are discussed.

Using two phase-change memory devices per synapse, a three-layer perceptron network with 164 885 synapses is trained on a subset (5000 examples) of the MNIST database of handwritten digits using a backpropagation variant suitable for nonvolatile memory (NVM) + selector crossbar arrays, obtaining a training (generalization) accuracy of 82.2% (82.9%). Using a neural network simulator matched to the experimental demonstrator, extensive tolerancing is performed with respect to NVM variability, yield, and the stochasticity, linearity, and asymmetry of the NVM-conductance response. We show that a bidirectional NVM with a symmetric, linear conductance response of high dynamic range is capable of delivering the same high classification accuracies on this problem as a conventional, software-based implementation of this same network.

Large-scale 3-D crossbar arrays offer a path to both high-density storage class memory and novel non-Von Neumann computation. However, such arrays require each non-volatile memory (NVM) element to have its own non-linear access device (AD), which must pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Using circuit-level SPICE simulations, we explore design constraints on crossbar arrays composed of a generic NVM element (+1R) together with the novel AD developed by our group, based on Cu-containing mixed-ionic-electronic-conduction (MIEC) materials. We show that power consumption during write, not read margin, is the most stringent constraint for large 1AD+1R crossbar arrays. As array size grows, in order to keep NVM write power-efficient, the voltage at which the AD “turns on” must outpace the NVM switching voltage. Failure to achieve this condition causes the total array power, injected into the array to ensure the success of the worst-case single-bit write, to greatly exceed the actual NVM write power. Extensive tolerancing results show that NVM switching current and other AD parameters (subthreshold slope and series resistance) are also important, but not to the same degree as AD and NVM voltage characteristics. We show that scaled MIEC devices (Voltage Margin $V_{m} \sim $ 1.54V) can support 1 Mb arrays for NVM switching voltages up to 1.2V, and that stacking two MIEC devices could enable $\sim 2.4\text{V}$ . The impact of $V_{m}$ variability is quantified—we show that there is minimal degradation in write power and read margin at variabilities (standard deviation in $V_{m}$ ) not very different from those already demonstrated experimentally.

A number of applications call for the organization of resistive non-volatile memory (NVM) into large, densely-packed crossbar arrays. While resistive-NVM devices often possess some degree of inherent nonlinearity (typically 3-30× contrast), the operation of large (>1000×1000 device) arrays at low power tends to require large (> 1e7) ON-to-OFF ratios between the currents passed at high and at low voltages. Such large nonlinearities can be implemented by including a distinct access device together with each of the state-bearing resistive-NVM elements. While such an access device need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device.We review our work on high-performance access devices based on Cu-containing Mixed-Ionic-Electronic Conduction (MIEC) materials [1–7]. (This version focuses only on the MIEC-based access device itself; previously-published longer versions of this work [8–10] also include more extensive surveys of competing devices as well.) These devices require only the low processing temperatures of the Back-End-Of-the-Line (BEOL), making them highly suitable for implementing multi-layer crossbar arrays. MIEC-based access devices offer large ON/OFF ratios (>1e7), a significant voltage margin Vm (over which current < 10nA), and ultra-low leakage (+ mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low (

Recyclable Thermoset Polymers The high mechanical strength and durability of thermoset polymers are exploited in applications such as composite materials, where they form the matrix surrounding carbon fibers. The thermally driven polymerization reaction is usually irreversible, so it is difficult to recycle the constituent monomers and to remove and repair portions of a composite part. García et al. (p. 732 ; see the Perspective by Long ) now describe a family of polymers formed by condensation of paraformaldehyde with bisanilines that could form hard thermoset polymers or, when more oxygenated, produce self-healing gels. Strong acid digestion allowed recovery of the bisaniline monomers.

Cross-linked micelles are used to generate large uniform mesopores in silsesquioxane-based thin films. To our knowledge, this is first time cross-linked micelles have been used for this type of application. The cross-linked micelles are fabricated from amphiphilic block copolymers to compatibilize large immiscible domains in the organosilicate. Measured pore sizes range from 20 to 30 nm depending on the porogen loading level. The spherical morphology is maintained over a wide range of porogen loading (5 to 50% wt.) as analyzed by scanning electron microscopy and ellipsometric porosimetry. The low-k porous films are stable in water as a result of the hydrophobic nature of the material, and the films can be stacked to form independent dielectric layers for numerous applications.

Magnetic nanoparticles (MNPs) provide a set of building blocks for constructing stimuli-responsive nanoscale materials with properties that are unique to this scale. The size and the composition of MNPs are tunable to meet the requirements for a range of applications including biosensors and data storage. Although many of these technologies would significantly benefit from the organization of nanoparticles into higher-order architectures, the precise placement and arrangement of nanoparticles over large areas of a surface remain a challenge. Herein, we demonstrate the viability of magnetic nanoparticles for patterned recording media utilizing a template-directed self-assembly process to afford well-defined nanostructures of magnetic nanoparticles and access these assemblies using magnetic force microscopy and a magnetic recording head. Photolithographically defined holes were utilized as templates to form assemblies of ferrimagnetic nanoparticle rings or pillars selectively over a large area (1 cm(2)) in just 30 s. This approach is applicable to other nanoparticle systems as well and enables their high-throughput self-assembly for future advanced device fabrication.

In recent years, a nano-electromachining (nano-EM) process based on a scanning tunneling microscope (STM) platform has been demonstrated. Nano-EM is capable of machining nano-features, under both, liquid dielectric (wet nano-EM) and air dielectric (dry nano-EM) media. The objective of this paper is to present a comparative study between the wet and dry nano-EM processes based on process mechanism, machining performance, consistency and dimensional repeatability of these two processes. The comparison of the two processes has been conducted at near field nano-EM, where the gap between the tool electrode and workpiece is 2 nm and the machining is performed at room temperature and pressure (macroscopically). The major differences in the process mechanism are due to the media at dielectric interface, the breakdown field strength and breakdown characteristics of two dielectrics and therefore, the material removal mechanism. It is reported that the material removal mechanism of wet nano-EM is associated with field emission-assisted avalanche in nano-confined liquid dielectric, whereas, the material removal mechanism in dry nano-EM is associated with field-induced evaporation of material. The differences have also been observed in the machining performance, dimensions of the machined features and repeatability of the nanoscale machined features. The self-tip -sharpening process with the continuation of machining has added several advantages to dry nano-EM over wet nano-EM in terms of dimensions of the nanoscale features, repeatability and machining performance.

A self-assembled magnetic recording medium was created using colloidal ferrimagnetic building blocks. Monodisperse cobalt ferrite nanoparticles (CoFe(2)O(4)) were synthesized using solution-based methods and then stabilized in solution using the amphiphilic diblock copolymer, poly(acrylic acid)-b-poly(styrene) (PAA-PS). The acid groups of the acrylate block bound the polymer to the nanoparticle surface via multivalent interactions, while the styrene block afforded the magnetic nanoparticle--polymer complex solubility in organic solvents. Moreover, the diblock copolymer improved the colloidal stability of the ferrimagnetic CoFe(2)O(4) nanoparticles by reducing the strong interparticle magnetic interactions, which typically caused the ferrimagnetic nanoparticles to irreversibly aggregate. The nanoparticle--polymer complex was spin-coated onto a silicon substrate to afford self-organized thin film arrays, with the interparticle spacing determined by the molecular weight of the diblock copolymer. The thin film composite was also exposed to an external magnetic field while simultaneously heated above the glass transition temperature of poly(styrene) to allow the nanoparticles to physically rotate to align their easy axes with the direction of the magnetic field. In order to demonstrate that this self-assembled ferrimagnet--polymer composite was suitable as a magnetic recording media, read/write cycles were demonstrated using a contact magnetic tester. This work provides a simple route to synthesizing stabilized ferrimagnetic nanocrystals that are suitable for developing magnetic recording media.

Nanomanufactured products with higher complexities in function, materials, scales and their integration demand an increasing need for advanced manufacturing tools. It is driven by applications such as ultra-dense memory, individualized biomedicine and drug delivery, molecular reading and sorting, and nanoscale circuitry. The tip-based nanomanufacturing (TBN) platform represents a potent gamut of processes for such applications – performing various nanoscale manufacturing operations including machining, depositing, patterning, and assembling with in situ metrology and visualization. This keynote paper presents a comprehensive overview of TBN processes based upon “nanotool tips” applying electrical, electrochemical, mechanical, electromagnetic and other forces to perform manufacturing operations.

Recently, a repeatable and scalable nanoscale electro-machining (nano-EM) process to produce sub-20 nm scale features has been demonstrated. In the presented research, the behavior of the liquid dielectric (n-decane) machining medium in nano-confinement (

Increasing circuit density in multilevel back-end-of line (BEOL) interconnects is necessary to improve integrated circuit performance and area scaling. Ultra low-k (ULK) dielectrics are used to minimize capacitance for lower power consumption and better capacitance-resistance (RC) performance. However, these materials pose integration and reliability challenges, which have limited our ability to scale the dielectric constant lower.1 Minimizing porosity, maximizing carbon content, and altering how carbon is bonded in porous SiCOH films reduces plasma-induced damage (PID) to the ULK and improves TDDB reliability, but these improvement must be balanced by maintaining other film properties such as elastic modulus. This paper describes one technique to achieve this combination of high carbon content and low porosity to allow k scaling while meeting integration and reliability requirements.

A nanoscale die-sinking electro machining (nano-EM) process has been developed on the scanning tunnelling microscope (STM) platform. The consistency of the features machined by the process depends on the quality of the tools used. A simple, fast, and reliable method has been developed using in situ STM to characterize nano-EM tool quality using current displacement (I-Z) spectroscopy curves. The tunnelling current from the tool was monitored as a function of the distance from the workpiece. The distance where the tunnelling current dropped to zero was correlated with the tool's ability to perform nano-EM and atomic resolution surface scans. The tools for which the tunnelling current dropped to zero at 4 Å from the workpiece resulted in consistent nano-EM and atomic resolution topographic scans. A quality criterion based on the I-Z method has been developed for nano-EM tools. This criterion can be extended to define the tool quality in probe-based machining processes and in the emerging field of molecular electronics.

There is a great need to produce nanoscale features on diverse and sometimes difficult-to-machine materials for electronic and bio-medical applications. This paper describes an electro machining (EM) process at nanoscale, implemented using a scanning probe platinum-iridium (Pt-lr) electrode tool (15-20 nm radius) in dielectric oil. The experiments were conducted by maintaining a gap of 2 nm between the tool and the work-piece. These experiments have successfully demonstrated that controlled and consistent machined features, as small as 10 nm in diameter, on atomically flat gold can be obtained. It is suggested that resonant tunnelling through dielectric oil molecules causes the removal of material.

Nanomechanical silicon cantilever beam test structures were fabricated from silicon-on-insulator wafers using electron beam lithography. A scanning probe system in the form of an atomic force microscope was used to measure their mechanical properties in a non-destructive evaluation approach. It is important to note that, despite the nanometer size of the silicon cantilever beams in the [100] direction, Young's modulus remained unchanged from the bulk value: 179 GPa. We believe that the fabrication processes did not induce any major structural modifications to the basic building blocks of silicon. Hence the Young's modulus was measured to be the same as that of the bulk silicon, which is important for designing predictable structures at nanometer scale.

The metallization of integrated circuits for high performance CMOS devices involves the use of copper with low-k or ultra low-k dielectrics to reduce RC delay and cross talk in devices. For the 90nm to 14 nm CMOS device nodes, conventional silicon nitride was replaced by new dielectric barrier low k materials such as SiCN, C-Rich SiCN and SiNO (1-6). As devices scale down to x film deposited by plasma enhanced CVD with TMS+NH3 is still robust down to around 15-20 nm thickness range. This paper presents the development of the second generation robust Low Hydrogen SiCN to enable cap thickness reduction to EXPERIMENT The low hydrogen SiCNx films were deposited in a commercial high throughput production worthy 13.6 MHz RF 300 mm Plasma Chemical Vapor Deposition process (PECVD) system at 350 C using a combination of Trimethyl Silane (TMS) + Ammonia (NH3) + Hydrogen precursors with excellent uniformity (1 sigma < 1 %). The as-deposited films were analyzed using various electrical , mechanical and chemical analyses to study the film's properties and compositions, Table 1. An oxidation resistance test (6) was done after the barrier film/copper blanket stack was annealed at 310°C for 24 hours in ambient atmosphere. Multi-level 7nm copper interconnect structures were built for Electro-migration (EM) and Time Dependent Dielectric Breakdown (TDDB) reliability measurement (150-300°C). RESULTS and DISCUSSION Table 1 summarizes SiCN and Low H SiCN cap film properties and device performance. Overall, the low H SiCN cap has better electrical, mechanical, and device reliability performance than the standard SiCN cap. The low H SiCN film has higher density, modulus, hardness and significantly higher compressive stress, both as-deposited and post 5 minutes direct UV cure. Compositional analysis shows that PECVD SiCNx cap films deposited with the addition of hydrogen precursor actually have less hydrogen than films deposited without hydrogen under the same optimized deposition condition. Film deposition rates decrease slightly at higher hydrogen flow rate in the TMS+NH3+H2 precursor chemistry. The reduced deposition rate and the hydrogen reduction in the film’s bulk are attributed to the increase removal (etching) of weakly bonded -Si-Hx and -N-Hy species in the film during the plasma deposition process. FTIR analysis shows that Si-C and Si-N bonding density increases in the low H SiCN dielectric, which is consistent with the increase in film density, modulus and harness. A minor reduction in the dielectric constant, similar breakdown voltage and reduced leakage are observed for the low H SiCN cap. Figure 1 shows a typical Scanning Transmission Electron Micrograph (STEM) of a 3nm Co/10 nm Low H SiCN cap on a Copper Metal2 7nm interconnect structure. This Cu/Co/Low H SiCNxcap structure achieves 4-10X better EM/TDDB reliability versus a similar structure with the standardcap (Table 1). A Scanning Electron Micrograph (SEM) of the patterned surface after annealing at 310°C for 24 hours in ambient atmosphere (Figure 1) shows that the 10 nm Low H SiCN cap has excellent Cu Oxidation properties with no sign of Cu Oxidation. CONCLUSIONS Low hydrogen SiCN dielectrics with improved mechanical, oxidation and Cu diffusion barrier properties versus standard SiCN were deposited using TMS, NH3 and H2. The new robust low hydrogen SiCN dielectric cap film showed a significant increase in Si-C and Si-N bonding density and a reliability performance improvement in 7 nm Cu interconnect structures at Acknowledgment This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. The author would like to thank B. Peethala for some analysis and A. Grill for discussion. REFERENCES [1] L. Xia, M. Naik, H. Xu, V. Zubkov, R. Bhatia, C. Peterson, M. Spuller, and H. M’Saad, Proceeding of Advanced Metallization for Devices and Circuits, (2006) pp. 169. [2] S.G. Lee et al, Jpn. J. Appl. Phys., 40, 2663 (2001). [3] Al Grill, Steve Gate, Son Nguyen, D. Priyadarshin, E Tood Ryan; Appl. Phys. Rev. 1, 011306 (2014). [4] Son V. Nguyen et al., Electrochem. Soc. Transaction 2014, Volume 61, issue 3, pp.17-28. [5] C.Yang et al., IEEE Electron Device Letter, Vol 33, No, 4, pp.588-560 (2012). [6] Son Nguyen et al., Electrochem. Soc. Transaction. 2010, Volume: 33, Issue: 12, pp.137-145. Figure 1

© 2014 AIP Publishing LLC. We report on the controlled removal of an amorphous Se capping layer from Bi2Te3 and Bi2Se3 topological insulators. We show that the Se coalesces into micron-sized islands before desorbing from the surface at a temperature of ∼150°C. In situ Auger Electron Spectroscopy reveals that Se replaces a significant fraction of the Te near the top surface of the Bi2Te3. Rutherford Backscattering Spectrometry and Transmission Electron Microscopy show that after heating, Se has been incorporated in the Bi2Te3 lattice down to ∼7 nm from its top surface while remaining iso-structural.

Using 2 phase-change memory (PCM) devices per synapse, a 3-layer perceptron network with 164,885 synapses is trained on a subset (5000 examples) of the MNIST database of handwritten digits using a backpropagation variant suitable for NVM+selector crossbar arrays, obtaining a training (generalization) accuracy of 82.2% (82.9%). Using a neural network (NN) simulator matched to the experimental demonstrator, extensive tolerancing is performed with respect to NVM variability, yield, and the stochasticity, linearity and asymmetry of NVM-conductance response.

Access Devices (1AD) for crossbar resistive (1R) memories are compared via circuit-level analysis. We show that in addition to intrinsic properties, AD suitability for 1AD+1R memories is strongly dependent upon (a) nonvolatile memory (NVM) and (b) circuit parameters. We find that (1) building large arrays (≥1Mb) with ≥10uA NVM current would require MIEC ADs and moderate NVM switching voltage (≤1.2V). (2) For all ADs high NVM voltages (>2V) are supported only at sub-5uA currents. AD improvements to expand this design space are discussed.

Numerical modeling is used to explain the origin of the large ON/OFF ratios, ultra-low leakage, and high ON current densities exhibited by BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-5]. Motion of large populations of copper ions and vacancies leads to exponential increases in hole current, with a turn-ON voltage that depends on material bandgap. Device simulations match experimental observations as a function of temperature, electrode aspect-ratio, thickness, and device CD.

Nanoscale silicon beams (∼3 μm long, 250 nm wide, and 193 nm thick) were implanted with Si ions at energies of 100 and 35 keV and a dose of 1×1015 ions/cm2 and then tested using an atomic force microscope. The Young’s modulus of fully amorphous silicon nanostructures (thus formed at 100 keV) was measured to be 134.5 GPa, and the modulus of bimaterial silicon nanostructures (amorphous and single crystal formed at 35 keV energy) was measured to be 150.3 GPa. Thus, the fundamental mechanical properties of 3D silicon nanostructures can be controllably modified using ion implantation at nanometer scale. This has major implications for nanoelectromechanical systems and related devices.

BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1–3] are shown to scale to the 100uA) currents of NVM writes can reach 15ns; NVM reads at typical (∼5uA) current levels can be ≪1usec.

BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1–4] are integrated in large (512 × 1024) arrays at 100% yield, and are successfully co-integrated together with Phase Change Memory (PCM). Numerous desirable attributes are demonstrated: the large currents (>200µA) needed for PCM, the bipolar operation required for high-performance RRAM, the single-target sputter deposition essential for high-volume manufacturing, and the ultra-low leakage (< 10 pA) and high voltage margin (1.5V) needed to enable large crosspoint arrays.

There is an ongoing need in the microelectronics industry to increase circuit density in multilevel back-end-of line (BEOL) interconnects to improve the operating speed and reduce power consumption. One way to maintain capacitance-resistance (RC) performance, without de grading yield or reliability is through introduction of porous ultra low-κ materials (ULK) as interlevel dielectrics (ILD). This paper presents the ability to tune ULK films through simple processing optimization steps to meet the specific integration requirements. Balancing composition of the film to minimize damage needs to be coupled with improving mechanical integrity for packing compatibility.

We show that bias polarity can greatly accelerate device failure in GST- based (GeSbTe) PCM devices, and trace this effect to elemental segregation, initially driven by bias across the melt but then enhanced during the crystallization process. Implications include device, pulse, and materials design for high endurance.

Nano-electromachining (nano-EM) is a process in which electric fields applied across sub-20 nm tool-workpiece gaps in organic dielectrics (n-decane C10H22 and n-undecane C12H26) are used to produce nanometer size features (8–80 nm) in electrically conductive materials. In order to improve the speed of nano-EM for manufacturing, utilization of pulse breakdown phenomena is studied. Linear behavior of Paschen curves for pulse breakdown demonstrated the predictability of pulse nano-EM process. The discharge current in the machining gap showed exponential decay behavior in the post-breakdown regime with certain delay. This delay in current recovery may present a limit to improving nano-EM production speeds and suggests a need for external pressurized dielectric flow over self-guided diffusion. Other notable effects such as adsorption compression limited dielectric diffusion and the variation in the recovery current with the tool-workpiece gap along with their engineering implications are discussed.

Phase change memory (PCM) could potentially achieve high density with large, 3Dstacked crosspoint arrays, but not without a BEOL-friendly access device (AD) that can provide high current densities and large ON/OFF ratios. We demonstrate a novel AD based on Cu-ion motion in novel Cu-containing Mixed Ionic Electronic Conduction (MIEC) materials[1, 2]. Experimental results on various device structures show that these ADs provide the ultra-high current densities needed for PCM, exhibit high ON/OFF ratios with excellent uniformity, are highly scalable, and are compatible with

For more than 50 years, the capabilities of Von Neumann-style information processing systems — in which a "memory" delivers operations and then operands to a dedicated "central processing unit" — have improved dramatically. While it may seem that this remarkable history was driven by ever-increasing density (Moore's Law), the actual driver was Dennard's Law: the amazing realization that each generation of scaled-down transistors could actually perform better, in every way, than the previous generation. Unfortunately, Dennard's Law terminated some years ago, and as a result, Moore's Law is now slowing considerably. In a search for ways to continue to improve computing systems, the attention of the IT industry has turned to Non-Von Neumann algorithms, and in particular, to computing architectures motivated by the human brain. At the same time, memory technology has been going through a period of rapid change, as new nonvolatile memories (NVM) — such as Phase Change Memory (PCM), Resistance RAM (RRAM), and Spin-Torque-Transfer Magnetic RAM (STT-MRAM) — emerge that complement and augment the traditional triad of SRAM, DRAM, and Flash. Such memories could enable Storage-Class Memory (SCM) — an emerging memory category that seeks to combine the high performance and robustness of solid-state memory with the long-term retention and low cost of conventional hard-disk magnetic storage. Such large arrays of NVM can also be used in non-Von Neumann neuromorphic computational schemes, with device conductance serving as the plastic (modifiable) “weight” of each “native” synaptic device. This is an attractive application for these devices, because while many synaptic weights are required, requirements on yield and variability can be more relaxed. However, work in this field has remained highly qualitative in nature, and slow to scale in size. In this talk, we will discuss our recent work on scaling NVM-based neural networks in size while quantitatively assessing engineering tradeoffs [1]. We demonstrate a 3-layer neural network of 164,885 synapses, each implemented with two PCM devices, trained on a subset (5000 examples) of the MNIST database of handwritten digits. A weight-update rule compatible for NVM+selector crossbar arrays is presented, as well as a “G-diamond” concept that illustrates problems created by nonlinearity and asymmetry in NVM conductance response. A neural network (NN) simulator matched to the experimental demonstrator allows extensive tolerancing. NVM-based Neural Networks are found to be highly resilient to random effects (NVM variability, yield, and stochasticity), but highly sensitive to “gradient” effects that act to steer all synaptic weights. Low “learning-rate” is shown to be advantageous for both high accuracy and low training energy. Both the SCM and the neuromorphic applications become more attractive as the NVM arrays become large. However, in order to enable large crossbar arrays, a highly nonlinear access device (AD) is also required (in addition to the NVM devices themselves). We will also review our past work on high-performance ADs based on Cu-containing Mixed-Ionic-Electronic Conduction (MIEC) materials [2]. These devices require only the low processing temperatures of the Back-End-Of-the-Line (BEOL), making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (>1e7), a significant voltage margin Vm (over which current [1] G. W. Burr, R. Shelby, C. di Nolfo, J. Jang, R. Shenoy, P. Narayanan, K. Virwani, E. Giacometti, B. Kurdi and H. Hwang, "Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element," IEDM Technical Digest, page 29.5, (2014). [2] R. S. Shenoy, G. W. Burr, K. Virwani, B. Jackson, A. Padilla, P. Narayanan, C. Rettner, R. M. Shelby, D. S. Bethune, K. Raman, M. BrightSky, E. Joseph, P. M. Rice, T. Topuria, A. J. Kellock, B. Kurdi, and K. Gopalakrishnan, "MIEC (Mixed-Ionic-Electronic-Conduction)-based access devices for non-volatile crossbar memory arrays," Semiconductor Science and Technology, 29(10), 104005, (2014).

The use of metallic lithium anodes enables higher energy density and higher specific capacity Li-based batteries. However, it is essential to suppress lithium dendrite growth during electrodeposition. Li-ion-conducting ceramics (LICC) can mechanically suppress dendritic growth but are too fragile and also have low Li-ion conductivity. Here, a simple, versatile, and scalable procedure for fabricating flexible Li-ion-conducting composite membranes composed of a single layer of LICC particles firmly embedded in a polymer matrix with their top and bottom surfaces exposed to allow for ionic transport is described. The membranes are thin (

Nanoscale confinement of dielectric molecules is expected to influence their breakdown mechanism in applications such as nanoprobe based machining, molecular electronics, and other related technologies. This Letter presents the first experimental study of the breakdown of nonpolar, nonthiolated liquid dielectrics in the nanometer regime and develops a field emission assisted avalanche based approach to model such behavior. The studies show that dielectric breakdown in the sub-20 nm regime is independent of the cathode materials and is dominated by the electron emission and atomic cluster migration due to the "sub-20 nm scale confinement of the liquid dielectric."

Internal stresses can cause de-lamination and fracture of coatings and structures and it is well known that ion-implantation can be used to control such behavior through modification of the stress. Here, however, we show that the unique ability of implantation to create controlled stresses in materials by altering both the chemical composition and mechanical properties, combined with an increase in the bending strength of materials, can used to create novel vertical nanostructures. Silicon cantilevers (beams), 193nm thick, 200nm wide and 3μm long, were implanted with carbon ions to create a buried SiCx layers. The internal stresses generated by implantation caused the beams to bend at angles ranging from 10 degrees to greater than 90 degrees, leading to unique vertical nanostructures. This method can be used to create 3-D nano electromechanical systems (NEMS).

Knowledge of the mechanical behavior of strategically important materials such as silicon at nano scale is the key for building next generation devices. In this paper, we investigate the Young’s Modulus of nanomechanical beams [1-8 mm long, 200-400 nm wide, and 193 & 255 nm in thickness] fabricated from silicon-on-insulator (SOI) wafers. The beams of different dimensions were defined in PMMA resist using e-beam lithography. A layer of chrome deposited using lift-off technique, acted as an etch-mask for silicon to fabricate the beams by using RIE. The samples were dipped in BOE (Buffered Oxide Etch) to etch the oxide underneath and the beams were released using critical point drying. Using a Scanning Probe System, nanomechanical beams were bent using AFM silicon tapping mode probes. A controlled amount of force was applied by varying the voltage applied to the Z-axis piezoactuator. The values of beam deflection and the net force applied enabled us to plot the Load vs. Displacement graph for the bending of the nanomechanical beams. Using Euler - Bernoulli beam bending equations, the Young’s Modulus of the Silicon beams was measured to be 174 GPa. This value agrees within 5% of the known value of bulk silicon Young’s modulus of 169GPa. Thus we conclude that the value of Young’s modulus of Si beams does not change when the size is reduced to nanometer regime.

In this paper the authors describe the design considerations including force and tolerance analysis and mechanism and tip design, for a novel, dynamic scanning probe microscopy tip directly insertable into today’s existing atomic force microscopy tools. This tool is the first of its kind and is a major step in the field of nanomanufacturing enabling the use of nanomechanical machining operations for nanostructure top-down manufacturing. The application of this device is the nanomechanical drilling and milling of III-V semiconductor substrates for various applications such as nanovias for electrical interconnection of next generation electronic and photonic applications, as well as reservoirs and capillaries for nano-fluidics. Results to date indicate that device performance parameters allow a normal drilling force of 25 μN, tangential drilling force of 35 μN, maximum rotational speed of 100,000 rpm, and minimum machined feature size of less than 200 nm. This device is currently being fabricated at Sandia National Laboratories, SUMMIT MEMS foundry and being packaged at the University of Arkansas, Fayetteville High Density Electronics Center (HiDEC).Copyright © 2002 by ASME

Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3?30? contrast), the operation of large ( 1000?1000 device) arrays at low power tends to require quite large ( 1e7) ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate ADs have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line?which would eliminate any opportunity for 3D stacking?has been difficult.We review our work at IBM Research?Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1?7]. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (), a significant voltage margin (over which current nA), and ultra-low leakage ( 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions 30 nm and thicknesses 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based ADs shows that their operation depends on mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low ( 1.2 V) switching voltages, stacking two MIEC devices can support large crossbar arrays for switching voltages up to 2.5 V.

The emergence of new nonvolatile memory (NVM) technologies—such as phase change memory, resistive, and spin-torque-transfer magnetic RAM—has been motivated by exciting applications such as storage class memory, embedded nonvolatile memory, enhanced solid-state disks, and neuromorphic computing. Many of these applications call for such NVM devices to be packed densely in vast “crosspoint” arrays offering many gigabytes if not terabytes of solid-state storage. In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selecteddevices greatly exceed the residual leakage through the nonselecteddevices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic. This article reviews progress made toward implementing such access device functionality, focusing on the need to stack such crosspoint arrays vertically above the surface of a silicon wafer for increased effective areal density. The authors start with a brief overview of circuit-level considerations for crosspoint memory arrays, and discuss the role of the access device in minimizing leakage through the many nonselected cells, while delivering the right voltages and currents to the selected cell. The authors then summarize the criteria that an access device must fulfill in order to enable crosspoint memory. The authors review current research on various discrete access device options, ranging from conventional silicon-based semiconductor devices, to oxide semiconductors, threshold switch devices, oxide tunnel barriers, and devices based on mixed-ionic-electronic-conduction. Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM.

The addition of a low frequency RF (LFRF) component during plasma-enhanced chemical vapor deposition of porous SiCOH ultra low-κ films allowed for the incorporation of higher carbon content without lowering the Young's modulus or increasing the dielectric constant. The porous SiCOH films typically contain carbon bonded into the silica matrix primarily as Si(CH3)x species. The low frequency RF increased the total carbon content by adding CH2 and –CH = CH- species with some reduction of Si(CH3)x species. It also altered the SiOx bonding structure by increasing network SiOx bonding at the expense of the suboxide, indicating an increase in SiOx crosslink density. Although higher carbon content usually lowers the modulus of porous SiCOH films, the modulus of the higher carbon films generated by LFRF did not decrease because of their increased network SiOx bonding.

There have been several cantilever-based actuators which provide movement in a direction transverse to the length of the cantilever. Here we describe a novel actuator which gives movement in the same direction as that of the length of the element. This is achieved by a curling up action of a bimetal like 'metal on silicon dioxide' straight element due to large differences in the coefficients of linear expansions and the high temperature which is obtained during the metal deposition.© (1999) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We have designed, fabricated and tested a balanced doubly suspended versatile, torsion and flexural, MEMS resonator structure. The doubly suspended structure has been used earlier for very precise high Q resonators but we wished to study the various vibration modes of such a structure. FEM analysis has been used to compute the most likely 6 modes and their frequencies of free vibration. These modes include flexure, torsion and mixed modes. The arms of the resonator are deposited with magnetic films so as to give desired bending/twisting moments to the structure. The location of the films decides the symmetry and thus result in one of the six vibrational modes that are predicted by the FEM analysis. This paper describes the design, fabrication and measurements on resonator structures made at TIFR.© (1999) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Mitigation of line edge roughness (LER) remains a significant practical issue for extreme ultraviolet (EUV) resist performance at 22 nm dimensions and below. The authors have applied a suite of experimental characterization techniques and simulation methods to a set of model EUV resists with the aim of strengthening fundamental understanding of the nature and origins of LER. The influence of resist film composition on LER has been evaluated for positive-tone chemically amplified polymer and NORIA molecular glass resists, and has been correlated the effects with surface roughness on resist films exposed at doses comparable to those at the image line edge. The effect of developer type on LER has been characterized using two distinct developer compositions that provide aqueous base positive-tone and organic solvent negative-tone processes. The time evolution of image roughness during pattern development has been visualized using interrupted development in a flow cell configuration that halts the dissolution ...

The relationship between the polycrystalline nature of phase change materials (such as Ge2Sb2Te5) and the intermediate resistance states of phase change memory (PCM) devices has not been widely studied. A full understanding of such states will require knowledge of how polycrystalline grains form, how they interact with each other at various temperatures, and how the differing electrical (and thermal) characteristics within the grains and at their boundaries combine through percolation to produce the externally observed electrical (and thermal) characteristics of a PCM device. We address the first of these tasks (and introduce a vehicle for the second) by studying the formation of fcc polycrystalline grains from the as-deposited amorphous state in undoped Ge2Sb2Te5. We perform ex situ transmission electron microscopy membrane experiments and then match these observations against numerical simulation. Ramped-anneal experiments show that the temperature ramp-rate strongly influences the median grain size. By truncating such ramped-anneal experiments at various peak temperatures, we convincingly demonstrate that the temperature range over which these grains are established is quite narrow. Subsequent annealing at elevated temperature appears to change these established distributions of grain sizes only slightly. Our numerical simulator—which models nuclei formation through classical nucleation theory and then tracks the subsequent time- and temperature-dependent growth of these grains—can match these experimental observations of initial grain distributions and crystallization temperature both qualitatively and quantitatively. These simulations show that the particular narrow temperature range over which crystallization occurs shifts as a function of temperature ramp-rate, which allows us to quantify the lower portions of the time-temperature-transformation map for Ge2Sb2Te5. Future experiments and extensions of the simulator to investigate temperature-dependent interactions between neighboring grains, and to study nucleation from within the melt-quenched amorphous state, are discussed.