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The complexity and cost of system-on-chip (SoC) designs keep increasing every year, which has progressively led to more opportunities for 2.5D System-in-Package (SiP) design. While 2.5D integration technology offers advantages for heterogeneous chiplet-based systems, it also poses challenges of a more complex overall design flow with limited EDA tools support, physical design optimization issues, interposer floor-planning difficulties and complex system-level verification. Furthermore, accurate inter-chiplet connection modeling, chiplet characterization and top-level simulation activities are also needed for comprehensive verification of SiPs. To tackle these challenges, we share an automated chiplet-based codesign flow: built on the backbone with standard EDA design tools, an automatic SiP register transfer language (RTL) generator is developed for top-level SiP netlist generation; inter-chiplet connection routing with chip assembly router and parasitic extraction tools; interposer design and bumps placement with the foundry defined redistribution layer (RDL).

The biological incubator is beneficial to the growth of organisms. In the environment, the plants can improve their disease resistance, the cultivation of seedlings and the promotion of seed germination efficiency. The kernel of the system is based on single chip ATmega2560 serving to receive data from various environmental sensors. The suitable growth conditions for organisms in the environment can be established. Using the data collection for a long time, a big data analysis is performed by techfarmers to effectively and quickly adjust suitable growth parameters. An APP software is also designed for real-time monitoring. A truth table is designed to determine the turn on/off quantity and time for system load. The proposed cultivation system may be used to achieve power saving purpose with multiple sets of low-frequency switches.

Automatic layout optimization is becoming an important component of the DfM work flow, as the number of recommended rules and the increasing complexity of trade-offs between them makes manual optimization increasingly difficult and time-consuming. Automation is rapidly becoming the best consistent way to get quantifiable DfM improvements, with their inherent yield and performance benefits for standard cells and memory blocks. Takumi autofixer optimization of Common Platform layouts resulted in improved parametric tolerance and improved DfM metrics, while the cell architecture (size and routability) and the electrical characteristics (speed/power) of the layouts remained intact. Optimization was performed on both GDS-style layouts for standard cells, and on CDBA (Cadence Data Base Architecture)-style layout for memory blocks. This paper will show how trade-offs between various DfM requirements (CAA, recommended rules, and litho) were implemented, and how optimization for memories generated by a compiler was accomplished. Results from this optimization work were verified on 45nm design by model and rule based DfM checking and by wafer yields.

To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented during final routing optimization. This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow. The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge to a clean design.

DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful, these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness. An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and silicon experiment results will be presented.

Unlike past semiconductor manufacturing processes, nanometer technology has seen an exponential growth of complex design rules and constraints. As a result, direct optical shrink of products between process nodes is becoming less feasible. To facilitate aggressive time-to-market requirements by re-using designs under new process technology, new CAD automation tools and methodologies have been developed. This paper describes a process shifting flow of 130nm custom layout to 90nm. Design challenges at the new process will first be overviewed, followed by EDA-assisted layout migration. Finally, productivity gains together with the design qualities will be shown on the implementation of a next generation Itanium@2 server chip.

The sections in this article are 1 General Methods For Yield Improvement in Semiconductor Manufacturing 2 Monitoring and Diagnosis at The Unit Process and Equipment Level 3 Monitoring/DIagnosis at the Process Flow Level