Search

We present a comprehensive study of area scaling for 22nm-logic-node routed metal/via layers as a function of route pitch and patterning strategy in both single-exposure (SE) and double-patterning (DP) regimes. For each candidate route pitch (88-56nm), we determine an optimal illumination scheme and develop layout rules for the metal layers. A perturbative area model is used to approximate the impact of the candidate rule set on area scaling. For the most promising SE case, we apply a novel 'source/design optimization' technique to further optimize illumination and rules, wherein we extend the source-mask optimization approach (1) by allowing design rules to vary in the analysis. We demonstrate that the optimal area scaling achievable with DP techniques can be vastly superior to SE, and therefore may justify the associated additional cost per wafer.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.

In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-optimized mask was generated for each designated illumination condition as the source was swept through various parameter settings in order to find the best combination of source and mask. This approach has been successfully applied to explore and select lithography processes and design rules for advanced semiconductor technology nodes. In Luminescent's latest implimentation of ILT-enabled SMO, the same Level Set Method used in the mask optimization is used in the source optimization; in other words, the source map is represented by a level set function. During the optimization process, the level set function evolves to achieve a minimized cost function, where the cost function is defined as the difference between aerial image and ideal image (MEEF and DOF can also be used in the cost function) via a gradient flow, and the gradient flow is based on the cost function itself. This flow is interlaceded with the mask inversion flow so that a simultaneous mask & source co-optimization is achieved. In this paper a number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of ILT-enabled SMO.

As design rules of advance devices shrink down, not only process-window budget of lithography process is getting tighter, but also CD control to target is more important especially for multiple tool process environment in HVM (High Volume Manufacturing). The tool induced CD bias or CD difference between tools are derived by minute amount of residual imaging parameters even though with strict control in system. The tool to tool CD mismatch is able to be reduced to nanometer or sub-nanometer scale for critical features of concern by using released tools such as LithoTuner PMFC TM (Pattern Matcher Full Chip). During the matching process, tunable imaging parameters such as pupil shape and stage tilt can be used as matching knobs. In this paper, CD mismatch due to film stack change on same exposure tool was studied to check feasibility of PMFC application. Also, CD variation and its impact on CD mismatch by focus error as amount of intrinsic system was investigated as well. By considering the focus impact on CD proximity bias via simple mathematical ways, the CD matching process could be more accurately performed and verified.

As patterns shrink to physical limits, advanced Resolution Enhancement Technologies (RET) encounter increasing challenges to ensure a manufacturable Pr ocess Window (PW). Moreover, due to the wide variety of pattern constructs for logic device layers, lithographically weak patterns (spots) become a difficult obstacle despite Source and Mask co-Optimization (SMO) and advanced OPC being applied. In order to overcome these design related lithographically weak spots, designers need lithography based simulator feedback to develop robust design rules and RET/OPC engineers must co-optimize the overall imaging capability and corresponding design lithography target. To meet these needs, a new optimization method called SmartDRO (Design Rule Optimization) has been developed. SmartDRO utilizes SMO’s Continuous Transmission Mask (CTM) methodology and optimization algorithm including design target variables in the cost function. This optimizer finds the recommended lithography based target using the SMO engine. In this paper, we introduce a new optimization flow incorpora ting this SmartDRO capability to optimize the target layout within the cell to improve the manufacturable process window. With this new methodology, the most advanced L/S patterns such as metal (k1 = 0.28) and the most challenging contact patterns such as via (k1 = 0.33) are enabled and meet process window requirements. Keywords: RET, manufacturable PW, SMO, SmartDRO , CTM, Design (Layout) Optimization

Application of atop-surface imaging(TSI) process by silylation to ArF lithography is desirable for ULSI production with minimum feature size for sub-120nm. We evaluated lithographic performances of non-chemically amplified positive TSI photoresist and chemically amplified negative TSI photoresist, both based on phenolic polymer. When off-axis illumination was used, 120nm and 110nm L/S patterns were obtained with non-chemically amplified resist(non-CAR) and chemically amplified resist(CAR) respectively. 100nm L/S patterns of CAR were obtained with strong off-axis illumination using binary intensity mask. CAR was superior to non-CAR in terms of lithographic performances, but inferior to non-CAR in terms of resist pattern collapse. Line edge roughness(LER) of CAR was sufficiently minimized by optimizing silylation bake temperature and it was comparable to that of single layer resist. For the prevention of resist pattern collapse in dry development process, the property of adhesion and resist rigidity is impor ant. This results can help the design of matrix resin of TSI resist for sub-100nm lithography.

HTF001 (Hyundai Thermal Flow Resist), a newly developed positive KrF resist for applying the resist flow process (RFP) to define sub-100nm contact hole (C/H) required at advanced gigabit-DRAM, consists of two kinds of polymer which have functional groups to cross-linking. Cross-linking reaction in HTF001 occurs at high baking temperature needed to shrink C/H size up to sub-100nm. The flow-characteristics and the deformation of C/H profile are greatly improved by applying HTF001. Extreme fine C/H (55nm) patterns applicable to 16G DRAM, successfully obtained from an original 200nm C/H patterns with KrF (248nm) lithography, show good pattern profiles without severe bowing, and still keep up the initial CD (Critical Dimension) uniformity after the resist flow. Moreover, it is successfully transcribed to vertical oxide C/H without CD bias, when we etch the oxide substrate of 5000A.

To overcome post exposure delay (PED) effect caused by airborne contamination, novel concept of rheological approach was introduced. By changing the polymer structures in resist solution, shear thinning resists were made. The method to make shear thinning resist includes, using of shear thinning solvent, modification of polymer structure, and temperature control of resist solution. Shear thinning resists exhibit good PED stability.

Recently reported ArF positive photoresists can be classified into three groups: derivative methacrylate copolymers (methacrylate resist), methacrylate copolymers functionalized with pendant alicyclic moieties (alicyclic resist), and cycloolefin-maleic anhydride copolymers (cycloolefin resist). Each system has its own advantages and drawbacks in the viewpoint of lithographic properties.Methacrylate resists have been used for the assessment of ArF lens performance. However, it is hard to apply them in real device process because of their low plasma-etch resistance. Previous studies have reported that alicyclic resists possess adequate etch resistance with the help of cyclic carbon units, however these resists show poor adhesion and seldom dissolve in 2.38% TMAH developer. The cycloolefin resists will be good candidate for addressing the trade-off between etch resistance and requisite material properties for lithographic performance because these resists, unlike methacrylate-based resists, contain large quantities of alicyclic structures directly in the polymer backbone and such properties as dissolution and adhesion can be readily controlled by incorporation of -COOH and -OH functional groups into cycloolefin structures.We have synthesized poly(2-hydroxyethyl 5-norbornene-2-carboxylate / t-butyl 5-norbornene-2-carboxylate / 5-norbornene-2-carboxylic acid / maleic anhydride; HNC / BNC / NC / MA) resists with a variety of functional groups and obtained lithographic performance by using ArF stepper(0.6NA). In this paper, we will describe the basic idea for designing of the novel cycloolefin resist and demonstrate lithographic capabilities, especially in terms of process window for 130nm feature. In addition, the etch resistance of this resist will be shown. We believe that off-axis illumination should be applied to 130nm device technology to obtain wider process window

The formation mechanism of tungsten (W) atoms in tungsten etching has been investigated with the SF 6 /Ar helicon plasma. The etch rate of W films decreases with increasing flow rate of Ar in the SF 6 /Ar gas mixture while the density of tungsten atoms increases as measured by optical emission spectroscopy. Tungsten films are rarely etched with pure Ar plasma. The density of tungsten atoms generated by a direct sputtering is much less than the one in SF6/Ar plasma. By comparing the etch rate with the relative intensity of W atom as a function of source power and bias power, it was found that tungsten atoms are mainly formed through the dissociation reaction of stable product, WF X (0 % x % 6), and further by electron impact. The loading effect in tungsten etchback can be suppressed by enhancing the redeposition of TiN V F. (y and z ≥ 0) by-products by increasing the source power. The suppression mechanism of the loading effect is investigated by an in situ monitoring of optical emission of tungsten atoms generated during overetching in tungsten etchback.

As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last three decades, DRAMs(Dynamic Random Access Memories) have been quadrupling in level of integration every three year. The 16 Mb DRAM (0.5 μm design rules) is into volume manufacturing. Early 64 Mb DRAM (0.35 μm design rules) manufacturing is now on target. Logic circuits follows a similar trend, although 2 or 3 years later. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC's (Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography and post optical lithography technology, such as E-beam lithography and X-ray lithography for the next century.

ArF excimer laser(λ=193nm) lithography is emerging following KrF DUV lithography(λ=248nm ). 193nm lithography has proven its potential for feature sizes down to 0.15μmlines/spaces patterns using high NA(O.6) because of resolution improvement. However, in practical use of ArF technology, there are problems involved in the properties of photoresist. To solve these problems, we synthesized ArF polymer resin, poly(2- (2-hydroxyethyl) carboxylate-5-norbornene / 2-t-butylcarboxylate-5-norbornene/2-carboxylic acid-5-norbomene/Maleic anhydride), all of the main chains are composed of alicyclic unit. 2-(2-Hydroxyethyl) carboxylate-5-norbornene was found as a very suitable adhesion promoter. Using this resist, 0.15μm L/S pattern was obtained at 14mJ/cm2 doses, using an ArF stepper on the developer, 2.38wt% tetramethyl ammonium hydroxide aqueous solution.

A new environmetally stable positive tone deep UV resist has been designed by incorporating basic units into a matrix polymer for stabilization toward airbone contaminants. Poly(3-(t-butoxycarbonyl)-1-vinylcaprolactam) (poly(BCVC)), and poly(3-(t- butoxycarbonyl)-1-vinylcaprolactam-co-t-butyl acrylate-co-hydroxystyrene) (poly(BCVC-co- TBA-co-HOST)) were prepared and evaluated as potential deep UV photoresists. 0.2μm line/space patterns were obtained for these resist systems using a KrF excimer stepper (NA 0.55) with a dose of 25mJ/cm2. And these resists did not change pattern profile after 2 hours post exposure delay (PED) time in which ammonia concentration was 5 ppb. 3-(t-Butoxycabonyl)-1-vinyl-2-caprolactam (BCVC) unit as a basic moiety can not only solve the amine contamination problem effectively, bul also improve the resolution of the resists. BCVC unit reduces the diffusion of acid and it results in sharp contrast at the interface between the exposed and unexposed areas. Therefore, adding BCVC unit in matrix polymer leads to the stabilization of the pattern profile and higher resolution.

In the case of silicone nitride film acid treatment can eliminate resist scum so that we can get clean resist patterns. The acid used, called Clean D treatment for photoresist strip, normally consists of a mixture of surphuric acid (80% H2O) and hydrogen peroxide(80% H2O). ESCA(Electron Spectroscopy by Chemical analysis) was used to examine the surface of the films after cleaning with the acid treatment and to monitor the change in atomic percents of the films with time. Considering all the analytical data, this acid treatment to silicon nitride makes the film surface oxide-rich resulting in forming barrier layer between substrates and protons from PAG(Photo Acid Generator). For BPSG(Borophosphorous Silicate Glass) films the mechanism of the formation of resist foot is quite different from that of silicon nitride. Improved resist profiles on BPSG were obtained by the dehydration bake. Therefore it could be speculated that the formation of resist scums on silicon nitride films are due to the nitrogen in films and on the BPSG moisture. Surface pretreatment by oxygen plasma was also reviewed. It is quite certain that these two methods, acid and O2 plasma treatments are very effective, economical and simple process. However, there are delay time effects after pretreating films unlike other conventional oxide capping layers. This problem will be also discussed in details.

We report that, based on our experimental data, lens heating (LH) impact on wafer image can be effectively controlled by using a computational method (cASCAL) on critical device layers with no request on tool time. As design rule shrinks down, LH control plays a key role in preventing the image deterioration caused by the LH-induced wavefront distortion during exposure. To improve LH prediction accuracy, 3-dimension structure of mask stack (M3D) is considered in calculating the electro-magnetic (EM) field that passes through the mask for full chip. Additionally, lens specific calibration (LSC) is performed on individual scanners to take the lens-to-lens variation into account. In data comparisons, we show that cASCAL performs very well as an ASCAL substitute, and that M3D and LSC improve the LH prediction accuracy of cASCAL.

A positive-tone wet silylation process for I-line lithography is developed, using safe solvents and the commercial photoresist AZ 5214E (by Hoechst). The process is capable of resolving 0.3 μm lines and spaces on photoresist. Various silylating conditions, solution concentrations and two silylating agents namely HMCTS and B(DMA)DS have been tried. Silicon concentration, focus and exposure latitudes have been defined.

The combination of off-axis illumination (OAI) schemes with ‘weak’ phase shifting techniques is promising to improve the process latitudes of both dense and isolated features. In this paper, the performance of this combination to print 0.25 μm poly levels for logic circuits is investigated experimentally and by simulations, using DUV stepper ( λ = 0.248 μm , 0.42 NA ). Various resist types have been addressed, mainly with respect to proximity issues.

Patterning of contact hole using KrF lithography system for the sub 90nm technology node is one of the most challenging tasks. Contact hole pattern can be printed using Off-Axis Illumination(OAI) such as dipole or Quasar or Quadrupole at KrF lithography system. However this condition usually offer poor image contrast and poor Depth Of Focus(DOF), especially isolated contact hole. Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip CD variation reduction. The insertion of SRAF in a contact design is mostly done using rule based scripting. However the rule based SRAF strategy that has been followed historically is not always able to increase the process window of these 'forbidden pitches' sufficiently to allow sustainable manufacturing. Especially in case of random contact hole, rule-based SRAF placement is almost impossible task. We have used an inverse lithography technique to treat random contact hole. In this paper we proved the impact of SRAF configuration. Inverse lithography technique was successfully used to treat random contact holes. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described. As a conclusion, we suggest methodology to set up optimum SRAF configuration with rule and inverse lithography technology.

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Source Mask Optimization techniques are gaining increasing attention as RET computational lithography techniques in sub-32nm design nodes. However, practical use of this technique requires careful considerations in the use of the obtained pixilated or composite source and mask solutions, along with accurate modeling of mask, resist, and optics, including scanner scalar and vector aberrations as part of the optimization process. We present here a theory-to-practice case of applying ILT-based SMO on 22nm design patterns.

As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of this study will demonstrate the lithographic performance contribution that can be obtained from these mask optimization techniques in addition to what source optimization can achieve.

The lithographic performance of phase shifting and transmission masks are compared. This paper describes the ultimate resolution and process latitudes, that can be obtained by combining a phase shift mask with the DESIRE process at 248 nm. Special emphasis is put on the influence of coherence. Both simulation and experimental results are given.

Multiple focus exposures[1], optimization of the partial coherence[2–4] of the stepper and the use of surface imaging[5] have been studied as possible ways to improve depth of focus and exposure latitude for deep-UV lithography at sub-0.5 μm dimensions. Simulation and experimental results are compared. The multiple focus technique gives a marginal improvement in depth of focus, but at the expense of resolution and exposure latitude. Surface imaging combined with higher coherence factors gives the best resolution with the widest latitude.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance and need to be enabled for production as one of the leading candidates for low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in production. In a prior publication [1], it has been shown at clip level that the Inverse Synthesizer (IS™) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT n eeds to be studied at full chip level with various aspects including mask data fracturing, MRC co nstraints, writing time, and inspection. The computation of ILT mask usually starts with the calcu lation of an optimized contoured mask then followed by manhattanization step to convert contour into horizontal-ver tical segments. By varying the segmentation length during manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of segmentation length impact on writing time and lithography perfor mance at full-chip is presented. MRC is another important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and inspectability at various selected MRC rules are also presented in the paper. Keywords: Inverse lithography technology (ILT), Sub-resolution assist feature (SRAF), Resolution enhancement technology (RET), Lithography simulation

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM and RET flow required to continue shrinking designs in the low-k1 lithography regime. The ability to model and minimize MEEF during lithography optimization and RET application is essential to obtain a usable process window (PW). In Inverse Lithography Technology (ILT), MEEF can be included in the cost function as a nonlinear factor, so that the inversion minimizes MEEF, in addition to optimizing PW and edge placement error (EPE). ILT has been shown to optimize masks for a given source. Using ILT for contemporaneous Source and Mask co-Optimization (SMO) can provide further benefit by balancing the complexity of mask and source. Results demonstrating the benefits of "MEEF-aware" ILT and SMO for advanced technology nodes are presented in this paper.

In this paper, an overview of Inverse Lithography Technology (ILT) based on Level Set Methods (LSM) is provided. Applications of ILT in the advanced lithography process are then shown for several different devices, including DRAM, SRAM, FLASH, random logic, and imaging devices. ILT is used to correct the main patterns, as well as automatically insert SRAFs using model-based mathematical methods. The process of SRAF generation in ILT is unified with the process of inversion. With the help of ILT, SRAFs can be inserted where physically needed, independent of source parameters or target patterns. Results that demonstrate the adaptive nature of ILT SRAF insertion capability are presented. Wafer verification results were collected by multiple advanced semiconductor manufacturing companies at advanced technology nodes, including 45nm and 32nm nodes, and compared with their current OPC solution. Final wafer results presented here demonstrate that ILT improves pattern fidelity, enlarges process window, and provides remarkable control for line-end shortening.

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

As mask feature size decreases, etch bias control during Cr and shifter etch becomes more critical factor in Embedded Phase Shifter Mask (EPSM) mask making processes. Since the etching characteristics of the shifter materials, Molybdenum Silicide (MoSi), are sensitive to etching surface condition, Critical Dimension (CD) performance of the shifter layer strongly depends on incoming surface condition from Cr etch. In this paper, lateral etch component of MoSi etch was investigated as a function of various substrate conditions so that a new in-situ plasma treatment was suggested to control the CD bias during MoSi etch. The CD performance was characterized within the surface treatment plasmas and also correlated with some plasma parameters and substrate temperature. As a result, it was found that plasma surface modification could be an in-situ technique to better control the shifter CD in EPSM process and an essential option for redundancy tools in mask production environment.

Evaluation of lithography process or stepper involves very large quantity of CD measurements and measurement time. In this paper, we report on a application of Scatterometry based metrology for evaluation of binary photomask lithography. Measurements were made on mask level with ODP scatterometer then on wafer with CD-SEM. 4 to 1 scaling from mask to wafer means 60nm line on wafer translates to 240nm on mask, easily measurable on ODP. Calculation of scatterometer profile information was performed by a in-situ library-based analysis (5sec/site). We characterized the CD uniformity, linearity, and metal film thickness uniformity. Results show that linearity measured from fixed-pitch, varying line/space ratio targets show good correlation to top-down CD-SEM with R 2 of more than 0.99. ODP-SEM correlation results for variable pitch shows that careful examination of scatterometer profile results in order to obtain better correlation to CD SEM, since both tools react differently to the target profile variation. ODP results show that global CD distribution is clearly measurable with less outliers compared to CD SEM data. This is thought to be due to 'averaging' effect of scatterometer. The data show that Scatterometry provides a nondestructive and faster mean of characterizing lithography stepper performanceprofiles. APSM 1st level (before Cr removal) 'dual-space' CDs and EPSM rectangular contacts were also measured with and results demonstrates that Scatterometer is capable of measuring these targets with reasonable correlation to SEM.

As mask pattern feature sizes shrink the need for tighter control of factors affecting critical dimensions (CD) increases at all steps in the mask manufacturing process. To support this requirement Intel Mask Operation is expanding its process and equipment monitoring capability. We intend to better understand the factors affecting the process and enhance our ability to predict reticle health and critical dimension performance. This paper describes a methodology by which one can predict the contribution of the dry etch process equipment to overall CD performance. We describe the architecture used to collect critical process related information from various sources both internal and external to the process equipment and environment. In addition we discuss the method used to assess the significance of each parameter and to construct the statistical model used to generate the predictions. We further discuss the methodology used to turn this model into a functioning real time prediction of critical dimension performance. Further, these predictions will be used to modify the manufacturing decision support system to provide early detection for process excursion.

As lithography mask process moves toward 45nm and 32nm node, phase control is becoming more important than ever. Both attenuated and alternating PSMs (Phase Shift Masks) need precise control of phase as a function of both pitch and target sizes. However conventional interferometer-based phase shift measurements are limited to large CD targets and requires custom designed target in order to function properly, which limits phase measurement. Imaging simulations, both, in a rigorous and a Kirchhoff regime, show the dependency of the phase in the image plane of a microlithography exposure tool on numerical aperture, polarization, and on the so-called balancing of the mask for features close to the size of the used wavelength. For these feature sizes, the image phase does not coincide with the etch depth equivalent phase calculated from the nominal depth and optical constants of the shifter material. Additionally, for PSMs generating phase jumps deviating from 180°, the resulting phase in the image plane of a microlithography exposure tool depends on the transmitted diffraction orders through the aperture of the imaging system. Consequently Zeiss, in collaboration with Intel, has started the development of a laterally resolving Phase Metrology Tool (Phame) for in-die phase measurements. In this paper we present this optical metrology tool capable of phase measurement on individual line/spaces down to 120nm half pitch. Alternating PSM, Attenuated PSM, Cr-less masks were measured on various target sizes and simulations were performed to further demonstrate the capability and implication of this new method to measure the scanner relevant phase in-die, taking into account NA, polarization, and rigorous effects.

Chemically amplified resist (CAR) performance can be greatly influenced by post apply bake (PAB) and post exposure bake (PEB) conditions. The difficulty with optimizing these conditions for photomask process is cost and time. In typical wafer CAR resist development, multiple wafer splits and skews can be rapidly processed with relatively low cost and fast turn around time, whereas in photomask processing each ebeam-written mask with a set of DOE conditions can be expensive and time consuming to produce. This paper discusses a novel mask design and testing methodology that allow for many combinations of PEB and PAB conditions to be evaluated with one mask. In brief, this methodology employs orthogonal PAB and PEB thermal gradients across a plate. Some thermal profile, darkloss, resist top down critical dimensions (CD), and SEM cross section image results will be shared and discussed.

Scatterometers are widely used for line/space or 2D structure measurements in both wafer and mask industries. This technology is now gaining more acceptance and is being applied 3D structures such as contacts and pads. Contact CDs and trench depth in photomasks are critical monitoring parameters in mask industry and are discussed here. We are reporting contact CDs and profile results measured from targets from Binary, PSM, and Crless plates. The strategies of model creation such as using simple trapezoid versus more advanced shapes affect how well SWA and footings can be measured and reported from these structures. We are reporting CD and profile information obtained with Scatterometer, and then comparing CD SEM, AFM, and cross section SEM. Multiple different modeling configurations were used with different levels of complexity, and we report on optimum modeling strategy to obtain profile information from 3D structures. The relationship between the modeling strategy versus cross correlation between different parameters is discussed. CD linearity, uniformity, and other correlation parameters to the reference CD SEM tool are reported. Target CDs ranged from 60nm up to 600nm. CD uniformity reported from Scatterometry is 20~30% less than that from CD SEMs. This CD uniformity improvement is due to the fact that scatterometer beam samples dozens to hundreds of samples and 'averages' profile parameters, thus eliminating local effect such as line edge roughness. Contact depth are also measur ed and compared to AFM, in which the bias between the two tools are usually around 3nm or less. In terms of smallest target CD measurable, in this paper we report routine measurement of small contacts with middle CD down to 65nm (bottom CD close to 50nm) with both RP and SE mode. Application of scatterometry method to mask contacts and pads leads to accurate and fast measurement of 3D profiles, and opens up possibility of in-line monitoring of profile information due to the higher runrate compared to traditional metrology tools. Keywords: contacts, scatterometry, metrology, binary, PSM, Crless.

Linewidth and etch depth control on the photomask is rapidly becoming a major concern in mask processing. In this paper, we report on a Scatterometry based metrology system that provides line width and etch profile measurements on Embedded PSMs on Intel's 65nm and 45nm node test masks. Measurements were made with Nanometric's Atlas-M reticle measurement system. Spectrum data obtained from plates were analyzed using Timbre Technologies’ ODP analysis software. We characterized the CD uniformity, linearity, sidewall angle and thickness uniformity. Significant reduction in time per measurement is achieved when compared to CD-SEM. ODP Scatterometry reported a 2x reduction in the CD Uniformity compared to that reported from the SEM. This reduction is typically due to outliers reported by the CD-SEM that is averaged out in ODP Scatterometry. Good correlation to top-down CD-SEM and cross-sectional SEM is reported. R-squared correlation of >0.99 (ODP scatterometry to top down CD-SEM) is reported. Profile measurements from ODP show excellent match to cross-section SEM. The data show that Scatterometry provides a nondestructive way to monitor basic etch profile combined with relatively little CD metrology lag.

Control of line width and profile is gaining more importance in photomask processes as the industry moves toward 45nm node and beyond. In this paper we report scatterometer measurements of CD and profile data from chrome-less mask profile processed using Intel's 65nm and 45nm node technology. As opposed to the highly charging nature of chrome-less plate during CD SEM measurements, scatterometry provides a non-charging optical alternative to measure critical CDs. As for trench depth measurement, scatterometry has big advantage over AFM with its much higher throughput (about 5 seconds vs. >2min). Since quartz plate is very transmittive to lights, we use eliipsometer-based scatterometry instead of conventional reflective-photometer based one. Parameters characterized in this study include line/space CD, contact CD, and trench depth. Correlation to top-down CD-SEM, cross-sectional SEM, and AFM is reported. Line CD uniformity reduction is more than 30% compared to that from CDSEM, due to averaging effect of scatterometry as well less lack of charging during measurements. Depth bias to AFM was around 3nm in both DCCD and FCCD height measurements we performed. The data show that Scatterometry provides a nondestructive way to monitor basic etch profile combined with relatively little time loss from measurement step.

As photomask complexity has increased, mask manufacturing has become significantly more challenging. Tightening specs on defect performance, resolution, and CD control have pushed mask manufacturing to achieve levels that nearly match wafer capabilities. To meet wafer manufacturing needs, mask production requires high yield and quick turn-around time, resulting in an increased demand for very high equipment reliability. In-line resist coating capability is important to meet these demands; both for robust 2nd level phase-shift coating processes, and the enablement of advanced 1st-level process development with new resists and new resist process conditions. Intel Corporation worked with Tokyo Electron Ltd (TEL) to bring one of the first CLEAN TRACK ACT M (ACT M) units through design, acceptance tests and into manufacturing. TEL's CLEAN TRACK ACT M is a resist coating tool based on the CLEAN TRACK ACT12 (ACT 12) wafer manufacturing platform, and contains multiple mask-specific modules including advanced softbake oven units, edge-bead removal modules, and cleaning systems. After setup and optimization, the tool shows impressive performance, (for example, within-plate thickness uniformity of < 8A (3s) for certain processes). The motivation of the tool layout is discussed thoroughly. Elements of the module designs and their performance are shown. The acceptance testing performance is presented and includes: cleaning capabilities, oven performance, thickness performance, coating defect levels and edge bead removal capabilities. Finally, there is a limited discussion of manufacturing performance.

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography. As the requirement on critical dimension (CD) and side wall profile control becomes ever stringent as minimum feature sizes keep shrinking following the Semiconductor Industry Association (SIA) roadmap, the patterning of the EUV mask absorber material, cost of ownership (COO) of mask, and the capability for defect free EUV masks become the crucial path in enabling the overall success of EUV lithography. The purpose of this study is to understand the etch characteristics in TaN-based EUV mask absorber etch, which will enable us to determine robust process condition in terms of CD performance and profile control. In this paper, CD bias performance in TaN-based EUV mask absorber etching is investigated within inductively coupled plasma (ICP) of fluorine-containing and chlorine-containing gas chemistries. The effects of etch parameters, such as plasma source power, bias power, and pressure, on the CD bias are evaluated through design of experiments (DOE). Some other etching characteristics like etch rate and selectivity are also correlated to the CD performance and etch profile to understand the basic etch mechanism in TaN etch. Latest etch results of the TaN-based absorber are also presented.

The effect of fluorocarbon polymer buildup on oxide etching was investigated by monitoring the reactor chamber under an O 2 /Ar plasma. Its effect on contact etching was also investigated by empioying a CF 4 /CHF 3 /Ar plasma. It was determined that the O 2 /Ar plasma was very useful for confirming polymer buildup on the inner chamber surface. This is because of an increased oxide etch rate by fluorine radicals, formed by the dissociation of the fluorocarbon polymer. Meanwhile, contact etching in a CF 4 /CHF 3 /Ar plasma with a high CHF 4 /CF 4 ratio caused a reduction in etch rate near the edge of the wafer (in some cases even an etch stop), a considerable loss of critical dimension, and higher etch selectivity to polysilicon. These various etch behaviors are attributed to the polymer buildup on the inner surface of the chamber.

In this paper, two negative-tone chemically amplified resists (CAR) are evaluated. The methodology and results are compared and discussed. The resists include EN-024M from TOK, and NEB 31 from Sumitomo. Both resists show high contrast, good dry etch selectivity, and high environmental stability. EN-024M showed good coating uniformity while NEB31 showed a coating uniformity problem. This was a round “dimple” approximately one centimeter in diameter of different thickness and density at the center of the plate. We addressed the “dimple” coating problem as described in the paper. Optimum PAB and PEB temperatures and nominal to maximum doses for isolated features were determined by running a matrix of PAB and PEB temperatures along with a dose series. We evaluated the process and compared the lithographic performance in terms of dose sensitivity, dose and bake latitude, resolution, resist profile, OPC (Optical Proximity Correction) pattern fidelity, CD uniformity, environmental stability, Line Edge Roughness (LER) and etching bias and resistance.

Improvements in the final uniformity of masks can be shrouded by error contributions from many sources. The final Global CD Uniformity (GCDU) of a mask is degraded by individual contributions of the writing tool, the Post Applied Bake (PAB), the Post Exposure Bake (PEB), the Develop sequence and the Etch step. Final global uniformity will improve by isolating and minimizing the variability of the PEB and Develop. We achieved this decoupling of the PEB and Develop process from the whole process stream by using “dark loss” which is the loss of unexposed resist during the develop process. We confirmed a correspondence between Angstroms of dark loss and nanometer sized deviations in the chrome CD. A plate with a distinctive dark loss pattern was related to a nearly identical pattern in the chrome CD. This pattern was verified to have originated during the PEB process and displayed a (Final CD)/ (Dark Loss) ratio of 6 for TOK REAP200 resist. Previous papers have reported a sensitive linkage between Angstroms of dark loss and nanometers in the final uniformity of the written plate. These initial studies reported using this method to improve the PAB of resists for greater uniformity of sensitivity and contrast. Similarly, this paper demonstrates an outstanding optimization of PEB and Develop processes.

High resolution etching of MoSi for photomask processing places new requirementson etching processes. As resist features are sized to 100nm and below, it is firstnecessary to duplicate these features first into a chrome over-layer. After resist isstripped, this chrome over-layer is used for etching MoSi. Both chrome and MoSietched profiles require near-vertical sidewalls, good CD (critical dimension)uniformity, good linearity, and CD mean-to-target (MTT). Additional requirementsof etched MoSi include minimal roughness on exposed quartz, selectivity to chromeand quartz, phase angle target and phase angle uniformity, etch depth globaluniformity, and etch depth uniformity as a function of feature size.An ETEC integrated process is used for the application of resist, patterning, and allsubsequent processing. Chemically amplified resist is patterned with the 50kVMEBES ® Quadra ™ or MEBES eXara ™ raster scan electron beam writer, allowing forpatterning of small features with vertical resist profiles. Plates are etched in a Tetra

In this paper, a process established with a positive-tone chemically amplified resist (CAR) from TOK REAP200 and Fujifilm Arch FEP171 and 50kV MEBES system is discussed. This TOK resist is developed for raster scan 50 kV e-beam systems. It has high contrast, good coating characteristics, good dry etch selectivity, and high environmental stability. In the mask industries, the most popular positive tone CAR is FEP171, which is a high activation energy type CAR. REAP (Raster E-beam Advanced Process) 200 is low activation energy type and new acetal protecting polymer. In this study, we compared to these different type resists in terms of contrast, PAB and PEB latitude, resist profile, footing, T-topping, PED stability, LER, Global CDU (Critical Dimension Uniformity) and resolution. The REAP200 Resist obtained 75nm isolated lines and spaces, 90nm dense patterns with vertical profile, and a good stability of delay time.

In the lithographic processing, application of a bottom anti-reflective coating (BARC) has proven to provide a number of benefits, such as elimination of reflective notching generated by reflections from highly reflective substrates, reduced swing effects caused by thin film interference, and therefore improved line-width control. To achieve such benefits, the organic BARC materials should have strong absorption at the exposure wavelength, high etch rate and matching to commercial chemically amplified resist. In design concept, the formulation of organic BARC material requires a minimum of two functional parts i.e., a chromophore to control the reflection and a cross-linking part to avoid intermixing with resist cast on it. In this paper, we report the performance of new organic BARC materials designed to work for lithographic applications at 248 nm as well as 193 nm simultaneously.

Electron beam (e-beam) proximity effect correction (PEC) has become a critical consideration with the reduction of feature sizes and the increasing use of optical proximity effect correction (OPC). PEC is accomplished on the 50kV MEBES eXara system with the embedded PEC (emPEC) technique, which is an automated version of GHOST. This method equalizes the background exposure by writing a fifth pass in the reverse tone of the four primary exposure passes. This compensates for the dose differences in the background due to backscattered electrons. The result is feature size control independent of the proximity and density of surrounding features, and independent of feature size. The method is simple and does not require additional computations for raster scan systems. A description of the method and its results for both coverage proximity effect correction (feature size deviation as a function of the surrounding exposure density) and CD linearity (deviation of different feature sizes) is presented.