Search

Your search keyword '"Kerner, C."' showing total 162 results

Search Constraints

Start Over You searched for: Author "Kerner, C." Remove constraint Author: "Kerner, C."
162 results on '"Kerner, C."'

Search Results

1. Real-World Maintenance Phase Persistence on Ustekinumab and Adalimumab in Ulcerative Colitis

8. SiCP Selective Epitaxial Growth in Recessed Source/Drain Regions yielding to Drive Current Enhancement in n-channel MOSFET

10. The acceptability and feasibility of a novel peer-led schoolbased physical activity intervention for adolescent girls: The girls' peer activity (G-PACT) project

11. WAVE PROPAGATION IN RANDOM MEDIA

13. The device architecture dilemma for CMOS technologies

14. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

17. Different in vivoand in vitrotransformation of intestinal stem cells in mismatch repair deficiency

19. 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

20. Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

21. Electrical demonstration of thermally stable Ni silicides on Si1−xCx epitaxial layers

22. Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

23. Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

24. Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology

25. The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

27. Carbon-based thermal stabilization techniques for junction and silicide engineering for high performance CMOS periphery in memory applications

29. Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability

30. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

31. Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $\hbox{La}_{2}\hbox{O}_{3}/\hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High-$\kappa$ Dielectrics and Si Channel

32. Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)

33. Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

36. Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

37. Addressing Key Concerns for Implementation of Ni FUSI into Manufacturing for 45/32 nm CMOS

38. Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

39. Optimization of HfSiON using a design of experiment (DOE) approach on 0.45V Vt Ni-FUSI CMOS transistors

40. FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production

42. Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

45. Superior N- and PMOSFET scalability using carbon co-implantation and spike annealing

47. NMOS and PMOS Metal Gate Transistors with Junctions Activated by Laser Annealing

48. Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics

49. Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

50. Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs

Catalog

Books, media, physical & digital resources