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This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.

This paper proposes a scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates as a master-slave flip flop. In test mode, the proposed scan design performs scan operation using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can be set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design, and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits.

This paper proposes a low area calibration technique for TDC using a variable clock generator for accurate on-line delay measurement. For proposed calibration, we choose a sensitizable path whose end point is connected to TDC. Next we sensitize the path multiple times using a variable clock generator to apply the time intervals to TDC one by one. The TDC measures the time intervals one by one. From the obtained measurement results we can estimate the effects of process variation and aging on measurement results of TDC, and thus we can get accurate on-line delay measurement result and accurate failure prediction. Because the technique does not require extra circuits, except the variable clock generator and the two 2-to-1 switches, the area cost of the proposed calibration is low. In addition, the proposed calibration technique can be applied to not only basic monotonic TDCs, but also TDCs of different architecture such as ring oscillator-based ones. Experimental results confirm that the error of calibration depends on the resolution of the used variable clock generator. Area overhead is 9.6 %, which is 169.6 % smaller than the conventional stochastic calibration.

This paper describes a time-to-digital converter (TDC) architecuture with residue arithmetic or Chinese Remainder theorem. It can reduce the hardware and power significantly compared to a flash type TDC while keeping comparable performance. Its FPGA implementation and measurement resuts show the effectiveness of our proposed architecture.

This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable System-on-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.

This paper describes a digital method of reducing timing mismatch effects in time-interleaved ADCs used in ATE systems: we use cross-correlation among channel ADC outputs to detect channel timing skew, and make successive-approximation adjustments to our proposed linear-phase-digital delay filter to compensate for the timing skew. Simulation results validate the effectiveness of the proposed method. We found that using multitone input signals with cross-correlation of outputs provided a more robust way of detecting timing skew than using a singletone input signal. Since our proposed approach is fully digital, it is reliable, and suitable for fine CMOS implementation.

This paper presents a theoretical analysis of the stochastic calibration of TDC using two ring oscillators. Designers of TDC with the calibration function have to decide the design parameters to guarantee the convergence of error and valid calibration time. The basic theory of the calibration is useful to decide these parameters and the policy on the calibration design. The performance of the stochastic calibration depends on the design parameters, the frequencies of the two ring oscillators, the number of the stages, the buffer delay, and so on. This work analyzes explicitly the relation between these parameters and the performance of the calibration with simulation-based analysis. Simulation results reveal that the convergence of the calibration is guaranteed when both of the cycles of the two ring oscillators are the prime cycles. The histogram of each bin converges to the corresponding buffer delay value in a well-behaved manner, the DNL measurement error decreases monotonically in proportion to the increase of the number of the times of the measurement. In other words, the required number of the measurement times is in proportion to the required accuracy of calibration. This result is applied to the calibration of VDL-based TDC, too.

High-speed digital LSIs such as CPU, graphic processing LSI, and System-on-a-chip, are indispensable for all the today's consumer electrics. However, such today's high performance LSIs require careful debugging for timing related errors and high quality delay fault testing for the dependability. This paper presents time-multiplexed on-chip delay measurement to realize fast and high quality timing error debugging and delay fault testing. According to the experimental result, the measurement time of the proposed method is 2.5 % of the conventional one.

This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate trees and a selector circuit. In addition, the area of SSG is lower than the conventional one. SSG is additional circuit which sends the transition from the output of the path under measurement to the embedded delay measurement circuit. Therefore, the area of the proposed system is lower. Because the area is low, the proposed method can be used for small-delay defect detection in manufacturing testing and failure prediction due to aging after shipment. We can apply the proposed delay measurement system to any embedded delay measurement circuit that measures the time difference between the two input signal transitions sent to the circuit. The evaluation shows that the area overhead is 16.54%. It is 6.62% smaller than the conventional method, and 8.41% larger than standard scan design.

This paper presents a low-area and short-time scan design for delay measurement using signature registers. The number of redundant latches is reduced utilizing X bits of test data for the delay measurement. After that, with the optimization of the scan chain routing, the scan chain length is reduced without decrease of the number of the measurable paths. These techniques keep the area overhead in the same order of that of the conventional scan designs for testing. In addition, the techniques further reduce the measurement time. Evaluation shows that the area overhead is 22.1% larger and 24.0% smaller than standard scan design and enhanced scan design respectively, which is in the order of scan designs for test. The measurement time is 90% shorter than that of standard scan design.

This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area, smaller data volume, and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18μm process shows that the area overhead of the proposed scan design is 32.2% smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively.