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With the development of multimedia and computer graphics technologies, virtual reality (VR) is attracting more and more attention from both the academic communities and industrial companies. A head-mounted display (HMD) is the core equipment of VR. It envelops the entire sight of the wearer and reacts to some specific actions, mainly the head movement. Different from common video watching or game playing, VR poses the strict requirement of immersion so interaction methods need to be carefully designed. The hotword-based interaction as a typical hands-free method is very suitable for VR scenarios. However, the traditional hotword detection methods use a microphone to permit audio signal analysis. They not only incur significant recording overheads but are also susceptible to the surrounding noises. Instead of using the audio signals, we propose a motion-based hotword detection method called Alohomora. A multivariate time series (MTS) classification is formulated for processing the sensor data from multiple dimensions and types of motion sensors. We use a word extraction method for extracting and selecting patterns from MTS of motion data. Then, a classification model is trained using those discriminative patterns and finally the hotword can be detected in time. Alohomora is purely based on the motion sensors in HMDs without using any extra components such as microphone. As head tracking is always necessary in VR applications themselves, the overhead of Alohomora is nearly negligible. Finally, through extensive experiments, the final detection accuracy of Alohomora can exceed 90%.

Video streaming takes up an increasing proportion of network traffic nowadays. Dynamic adaptive streaming over HTTP (DASH) becomes the de facto standard of video streaming and it is adopted by Youtube, Netflix, and so on. Despite of the popularity, network traffic during video streaming shows an identifiable pattern which brings threat to user privacy. In this paper, we propose a video identification method using network traffic while streaming. Though there is bitrate adaptation in DASH streaming, we observe that the video bitrate trend remains relatively stable because of the widely used variable bit-rate (VBR) encoding. Accordingly, we design a robust video feature extraction method for eavesdropped video streaming traffic. Meanwhile, we design a VBR-based video fingerprinting method for candidate video set which can be built using downloaded video files. Finally, we propose an efficient partial matching method for computing similarities between video fingerprints and streaming traces to derive video identities. We evaluate our attack method in different scenarios for various video content, segment lengths, and quality levels. The experimental results show that the identification accuracy can reach up to 90% using only three-minute continuous network traffic eavesdropping.

At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. As a result, the delay of an otherwise fault-free path may exceed the functional clock period. Such thermal emergencies can thus lead to over-detection and undue yield loss during testing. Their effects will be more severe for small-delay defects (SDDs), which target to sensitize the long paths in a circuit. In this paper, we quantify, for the first time, the impact of thermal emergencies on SDDs and provide a solution to mitigate them. The proposed method is based on: 1) a new thermal-aware (TA) path-selection method, 2) a TA test-ordering method, and 3) an effective scan architecture and a test-application scheme. Experimental results on benchmarks demonstrate that the new method can significantly reduce the number of over-detections of SDDs.

The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new poweraware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time. Since enabling only a subset of scan flip-flops to capture test responses in one cycle compromises the fault coverage, we propose a new method to reduce the fault coverage loss. First, we use a more accurate notion, spoiled nodes, instead of violation edges used in previous works to analyse the ependency of flip-flops, then we use simulated annealing(SA) mechanism to find the best combination of these flip-flops while considering the clock trees' impact. To the best of our knowledge, this is the first work to make shift and capture power in a controllable way with minimum fault coverage loss, small test-data volume and no extra hardware overhead for at-speed transition fault test. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed method.

With the chip size entering the micro-nano level, the increasing power consumption during the chip testing process becomes the bottleneck of chip production and testing. Prior work has been mainly focused on reducing power dissipation in either shift cycle or capture cycle, however, there has been limited work on reducing the peak power in both shift and capture cycles at the same time. Moreover, there has been no work on the problem of capture power controllability. This paper proposes a new power-aware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time with small area overhead. Meanwhile, we devise sophisticated algorithms of dependency checking and scan segments partitioning, which can directly reduce simultaneously switching activity of flip-flops by iterative optimizing scan segments grouping. To the best of our knowledge, this paper is the first of its kind to study the problem of power controllability considering both structure dependency and clock trees' impact. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed architecture.

The rapid growth in CMOS technology enables the technology of three-dimensional (3D) SoCs to be a promising approach for extending Moore's Law. Although the benefits supplied by 3D integration, managing test architecture design and reducing test cost are crucial challenges. Some powerful automatic test equipments (ATEs) that support different speed rate channels come into people's vision. In this paper, we propose a dual-speed TAM architecture optimization for 3D SoCs with hard dies, including a novel algorithm to minimize test time for both mid-bond and post-bond testing according to this new TAM architecture. Experimental results on ITC'02 SoC benchmark circuits show that our proposed scheme reduces total test time by around 35% on average compared with one baseline solution.

Three-dimensional (3D) SoC is becoming one of the most promising approaches for extending Moore's Law. However, managing test optimized scheme to reduce the cost of 3D SoCs is a significant challenge. In this paper, we propose a cost-effective optimized scheme of 3D SoCs for pre-bond test based on a generic cost model we defined. Both test time and number of TSV are considered in our novel scheme. Experimental results on ITC'02 SoC benchmark circuits show that our scheme is superior to one baseline solution and can effectively achieve good performance on test optimization.

In this work, we propose a novel scan architecture for 3-D ICs by considering the interconnection overhead of through-silicon-vias (TSVs). Since hotspots in 3-DICs often cause performance and reliability issues, we also developed a new test ordering scheme to avoid applying test vectors that could worsen the temperature distribution. Experimental results show that the peak temperature can be lowered by 20% by the 3-D scan tree architecture. When combined with the test ordering scheme, the 3-D scan tree can further reduce peak temperature by over 30%.