Search

We investigate the effects of hydrogen radical treatment on piezoresistance coefficients of germanium under uniaxial stress up to ±500 μ strain over the temperature range −30 °C to 25 °C. Hydrogen radicals are produced by hydrogen gas (99.99%, 2.7 kPa) on a hot tungsten catalyst (1800 °C). The gauge factor and majority carrier on non-dope germanium dramatically changed from n- to p-type after the hydrogen radical treatment. The results suggest that the piezoresistance coefficients of germanium are seriously affected by vacancy-related levels around the midgap, which behave as donors or acceptors depending on the Fermi level and are passivated by the hydrogen radicals.

Sheet resistance ( ${R_{sheet}}$ ) reduction of a-few-layered molybdenum disulfide (MoS2) film using sputtering is investigated in this study. To enhance the carrier density, chlorine (Cl2) gas excited by inductively coupled plasma is introduced as a substitute for sulfur. To electrically activate the Cl dopants and simultaneously prevent out-diffusion of sulfur, a furnace annealing was performed in sulfur-vapor ambient. Consequently, the ${R_{sheet}}$ in the MoS2 film with the Cl2 plasma treatment remarkably reduced by one order lower than that without one, because of the activation of Cl dopants in the MoS2 film.

Vertical PNP bipolar transistor test structures were fabricated and measured, attempting to electrically obtain information on carrier lifetime in the voltage-supporting base region of Insulated Gate Bipolar Transistors (IGBTs). Owing to the structural similarity, the test structures and functional IGBTs can be integrated on the same wafers, making it possible to directly correlate lifetime data and IGBT characteristics. To solve a problem of leaky backside PN junction, common base current gain of the test devices was measured without applying a reverse bias between the collector and base terminals, which suppressed the leakage to an acceptable level. A simple analytical formula to convert the current gain to hole lifetime in the N-type base region was proposed and used, that takes into account the existence of a commonly used N-buffer layer adjacent to the backside P-collector layer. The validity of the formula was confirmed using TCAD simulations. This method was applied to IGBT wafers with two different wafer thicknesses (i.e., base lengths): $120~{{\mu }}\text{m}$ and $360~{{\mu }}\text{m}$ . Consistent lifetime values extracted in spite of the largely different thicknesses supports the validity of the proposed lifetime estimation method.

Domain-switching kinetics of 5 mol% Y-doped HfO2 metal-insulator-metal (MIM) capacitor was characterized. The changes in polarization indicate the polarization reversal in HfO2. In this research, we show the polarization reversal of an 20-nm-thick Y-doped HfO2 deposited by atomic layer deposition (ALD) by switching the applied voltage (2.6 to 4.6V) and the pulse duration (1μs to 500μs). We use the measurements of Kolmogorov-Avrami-Ishibashi (KAI) model to extract the minimum switching time of the domains. Introduction Ferroelectric HfO2 layer has attracted attraction in CMOS and memory applications owing to its scaling ability and process compatibility. It has been demonstrated that doping of foreign elements, including Zr, Si, Al, Y, atoms under post-deposition annealing (PDA) or post-metallization annealing (PMA) induces the ferroelectricity in HfO2 [1]. The switching dynamics of ferroelectric Al- and Zr-doped HfO2 metal-insulator-metal (MIM) capacitors has been well-modeled by nucleation limited switching (NLS) model, where multigrain polarization takes place assuming a distribution in the switching time [2, 3]. In this study, we apply the KAI model to fit the switching dynamics of Y-doped HfO2 MIM capacitor using the following equation, , △P=Ps*(1-exp{-(t/τ)β }) where △P, P s, τ and β are the partial, saturation polarization, switching time constant and a fitting parameter, respectively [4]. Experiments An MIM capacitor with a 20-nm-thick 5 mol% Y-doped HfO2 film was fabricated by atomic layer deposition (ALD). The top and bottom electrode were both W deposited by sputtering. PMA was then carried out at 500 oC for 1 minute. Typical polarization-voltage (P-V) hysteresis is shown in fig. 1, where a remanent polarization (P r) of 12 mC/cm2 was obtained. A voltage waveform shown in fig. 2 was applied to the electrode to measure the polarization reversal of the devices after certain polling process. Polarization reversal was extracted by applying pulses with various height ranging from 2.6 to 4.6 V and width from 1 ms to 500 ms followed by half P-V measurement. Results and discussions Fig 3 shows measured partial polarization with different pulse width and voltage. As the pulse width increases, △P increases, indicating that a certain time is required to fully switch the domains. Data fit using the KAI model has well reproduced the measured data, indicating the presence of multigrain switching. However, a β of 0.6 to 0.8, which is smaller than those of Zr-doped HfO2 (typically b=2.1), needs to be used to fit the data. This may imply the difference in the domain size among dopants incorporated in the HfO2 layer. Conclusion Switching dynamics of ferroelectric Y-doped HfO2 MIM capacitors has been measured. The device has shown to follow the multidomain switching based on KAI model as is explained for Zr-doped HfO2 ones, except for the difference in the fitting parameter. References [1] J. Müller, et al., J. Appl. Phys., 110, 114113 (2011). [2] S. Zhukov, et al., Phys. Rev. B., 82, 014109 (2010). [3] C. Alessandri, et al., IEEE Electron Dev. Lett., 39, 1780 (2018). [4] N. Gong, et al., J. Appl. Phys., 112, 262903 (2018). Figure 1

Zirconium disulfide (ZrS2)—an attractive next-generation channel material because of its high mobility—is stabilized in the air by a zirconium dioxide (ZrO2) film which functions as a high-k film in MISFET. We fabricated high-k/PVD-ZrS2 stacks with a self-oxidized ZrO2 film as an interfacial layer; their chemical properties were analyzed to clarify how each fabrication process affects the ZrS2 under the oxide film. The results clarified that sulfur vapor annealing (SVA) is critical for fabricating high-quality physical vapor deposition (PVD) ZrS2 films and that the change in surface potential of the ZrS2 films due to interface dipoles between the high-k and Zr-compound films is suppressed with scaling of high-k thickness. The SVA with high-k films also prevents degradation of crystallinity and stoichiometry, enhancing the quality of the ZrS2 films without affecting their surface potential. These achievements enable us to control the threshold voltage in ZrS2 MISFETs.

Process robustness of ferroelectric HfO2 films formed by dopant-laminated structure is investigated. Ferroelectric hysteresis obtained by the sub-monolayer Y2O3 laminated structure confirms that entire doping to the HfO2 films is not indispensable to stabilizing the ferroelectric phase. The Y-laminated HfO2 capacitors show robustness against the oxygen plasma exposure time, in contrast to the positive hysteresis shift for uniformly doped HfO2 ones. The number of switching cycles was increased, presumably owing to the reduction of oxygen vacancies associated with the incorporated dopants. Moreover, the leakage current showed a reduction with a higher breakdown voltage.

Transition metal dichalcogenides (TMDC) have remarkable properties for the next generation of electronic devices [1]. A complementary metal-oxide-semiconductor (CMOS) inverter consisting of pairs of p-type and n-type field-effect transistor (FET) is a fundamental building block in modern digital electronics [2]. Therefore, realization of both p-type and n-type FETs based on semiconducting TMDC is of particular importance. Among various semiconducting TMDC, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [3]. These prominent features of WSe2 motivates the fabrication and characterization of a CMOS inverter. One of the significant challenges is to develop a high-gain CMOS inverter for operation at a low power supply voltage (Vdd) for future low power digital electronics. Previous studies on a WSe2 CMOS inverter were limited to operation with a low gain of 3 or a high Vdd of more than 1 V under conditions of relatively low gate capacitance and degraded interfacial properties [3-5]. This study addressed these issues by developing a doping technique and gate stack technology to demonstrate the high-gain with low-Vdd operation of a WSe2 CMOS inverter [6]. The focus is on the doping technique of both electrons and holes to a WSe2 layer by simple spin-coating. Of particular interest in this study is the impact of gate stack technology on the CMOS inverter characteristics in low-Vdd operation. In this study, a hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is applied to a WSe2 CMOS inverter for high-gain low-Vdd operation since superior interfacial properties with high gate capacitance have been reported in molybdenum disulfide (MoS2) FETs. For p-type WSe2 FETs, the fluoropolymer CYTOP (AGC, CTX-809A) was applied since polarization in CYTOP due to the difference in electronegativity between C–F bonds generates holes in WSe2. On the other hand, poly(vinyl alcohol) (PVA) was utilized for n-type WSe2 FETs because positive charges in PVA accumulates electrons in WSe2. The resin solutions of both CYTOP and PVA were purchased from a commercial supplier. A heavily doped p-type silicon substrate (p+-Si) was thermally oxidized to form a 60 nm thick silicon dioxide (SiO2) layer for the global back-gate architecture. Palladium (Pd) and gold (Au) as the source and drain contacts for p-type and n-type WSe2 FETs were fabricated by the lift-off process, respectively. An aluminum (Al) gate was prepared and a hybrid SAM/AlOx gate dielectric was formed by oxygen (O2) plasma and an immersion process. After that, mechanically exfoliated WSe2 was transferred with a poly(dimethylsiloxane) (PDMS) stamp. Finally, CYTOP and PVA were deposited by spin-coating for p-type and n-type WSe2 FETs, respectively. Figures 1 (a) and (b) show the Id–Vg characteristics of fabricated FETs. For the p-type WSe2 FET, a small SS of 78 mV/dec and an on/off ratio of about 106 order were observed. On the other hand, the Id–Vg characteristics of the n-type WSe2 FET were degraded compared with those of the p-type WSe2 FET because of the Schottky contacts. Figures 2 (a) and (b) show the transfer characteristics and gain as a function of Vdd in CMOS inverter. The gain of the CMOS inverter increased to as high as 9 at Vdd of 0.5 V. Figure 3 shows the benchmark of this study. Our proposed concepts enabled the operation with high gain at a low Vdd as low as 0.5 V for the WSe2 CMOS inverter, which had not been realized in previous studies. The dangling-bond-free and ultrathin SAM/AlOx gate dielectric has an important role in the low-Vdd operation of the WSe2 CMOS inverter. This study opens up interesting directions for the research and development of TMDC-based devices and circuits. References [1] Q. H. Wang, K. K. Zadeh, A. Kis, J. N. Coleman, and M. S. Strano, Nat. Nanotechnol. 7, 699 (2012). [2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices (Cambridge University Press, Cambridge, 1998). [3] L. Yu, A. Zubair, E. J. G. Santos, X. Zhang, Y. Lin, Y. Zhang, and T. Palacios, Nano Lett. 15, 4928 (2015). [4] C.-S. Pang and Z. Chen, 2018 76th Device Research Conf. (DRC), p. 1, 2018. [5] M. Tosun, S. Chuang, H. Fang, A. B. Sachid, M. Hettick, Y. Lin, Y. Zeng, and A. Javey, ACS Nano 8, 4948 (2014). [6] T. Kawanago, T. Matsuzaki, R. Kajikawa, I. Muneta, T. Hoshii, K. Kakushima, K. Tsutsui, and H. Wakabayashi, Jpn. J. Appl. Phys. 61, SC1004 (2022). Figure 1

Advanced logic devices have already reached a 5-nm technology node, which features a FinFET in Fig. 1 (a) and a new channel material of high mobility for p-type operation [1] . New structures and materials are expected to further continue a device scaling and performance enhancement. Advanced LSIs are announced to be improved by nano-sheet structures to enhance W eff /W footprint for 3-nm technology node in Fig. 1 (b) , expected to reduce a p/n isolation width using fork sheet structures for 2-nm technology node in Fig. 1 (c) , and imagined to reduce an area of CMOS inverter using complementary p/n-stacked structures for 1-nm technology node in Fig. 1 (d) [2 , 3] .

An enhancement-mode (E-mode) AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) with La2O3/SiO2 gate insulator is investigated for high power application. The La2O3/SiO2 composite oxide formed amorphous La-silicate after post deposition annealing. Good oxide film quality and excellent La-silicate/AlGaN interface properties were achieved as evidenced by the capacitance–voltage (C–V) curves and hysteresis effect of the La-silicate on AlGaN/GaN metal–oxide–semiconductor capacitors. As a result, the E-mode AlGaN/GaN MIS-HEMT with La-silicate gate insulator shows good threshold voltage (Vth) stability and demonstrated only slightly increase in the dynamic on-resistance (Ron) after high drain bias stress test. The device also exhibits high current density of 752 mA/mm, high maximum transconductance of 210 mS/mm, low subthreshold swing of 104 mV/decade, and ION/IOFF = 107 when tested at VDS = 10 V. Furthermore, low on-resistance of 7.6 Ω mm, high breakdown voltage of 670 V, and excellent delay time of 4.2 ps were achieved, demonstrating the La-silicate MIS-HEMTs have the potential to be used for power electronic applications.

A high Hall-effect mobility of 1,250 cm2V1s−1 is achieved in ZrS2 film as a two-dimensional semiconductor. A large-area atomic-layered polycrystalline ZrS2 film was obtained by sputtering and sulfurization. It was confirmed that a layered ZrS2 film on a SiO2/Si substrate was successfully achieved by a high-temperature sputtering and sulfur compensation process. We demonstrated that the Hall-effect mobility and the carrier density were greatly improved to 1,250 cm2V−1s−1 and $8.5 \times 10^{17}$ cm−3, simultaneously. High-mobility two-dimensional ZrS2 film is a strong candidate for advanced MISFETs.

Low-carrier density and high-crystallinity molybdenum disulfide (MoS2) films were fabricated by low-temperature and clean process based on a UHV RF sputtering system. This paper focuses on improving crystallinity and reducing the number of sulfur defects of sputtered-MoS2 film. We have fabricated MoS2 films at lower than 400°C using the sputtering and H2S post-deposition annealing processes. Consequently, MoS2 films with high crystallinity and appropriate S/Mo ratio were obtained. Eventually, a low carrier density of 3.5 × 1017 cm-3 and the Hall-effect mobility of 12 cm2 V-1 s-1 were achieved.

Ferroelectric materials have been utilized for non-volatile memory applications [1]. Recently, Al1-x Sc x N (ASN) films were reported to exhibit ferroelectricity with a high remnant polarization of over 100 µC/cm2 which is attractive for future non-volatile memory [2]. The feasibility of FeRAM application has been confirmed based on material and electrical properties [3]. One of the issues of ASN films is the lack of reliability and endurance properties, as the number of switching cycles of 104 to 105 is the typical endurance of the ASN films before breakdown [4]. In this study, we infer the gradual change in the ASN film upon switching cycles. A 50-nm-thick ASN film with x of 0.22 was characterized with TiN electrodes at top and bottom. The as-fabricated film is self-polarized in an upward direction; the negative voltage applied to the top electrode triggers the switching reversal. Capacitance-voltage (C-V) characteristics, double sweeping the voltage to the negative, and then to the positive directions, were used to observe the switching voltage. A sinusoidal wave with an amplitude of 28 V at 2 kHz was used to switch the capacitor, ending with a positive voltage applied to the top electrode. The C-V curve for the as-fabricated sample (fresh), shown in figure 1, showed only a single peak capacitance for each sweep. The voltage at the peak capacitance during the negative sweep shifted from -20.8 to -17.4 V from the first to third sweep, larger than the shift during the positive sweep. This indicates that the switching voltage, or the coercive field, was reduced during the first negative sweep. After stressing the sample by 103-cycle switching, the C-V curve revealed two capacitance peaks in the negative direction, as shown in figure 2; the peak at -20.2 and -15.2 V are referred to as the peaks obtained in the first and third sweeps for the fresh device. The capacitance peak at -20.2 V gradually decreased moving to merge to the peak at -15.2 V. During this transition, little change of the peak in the positive region was observed, indicating that a gradual transformation in the ASN film upon switching reversal is happening only when the film is switched from upward to downward direction. We hypothesized the creation of nitrogen-vacancy (VN) during the switching, facilitating the movement of N atoms to reduce the coercive field. One can understand that the transformation is completed during the C-V measurement for the fresh sample as the time for the measurement is long. In conclusion, we observed a gradual change in the switching voltage upon switching reversal. A lower coercive field was found to gradually appear after switching, decreasing, and shifting the initial coercive field. References [1] T. S. Böscke, et al., Appl. Phys. Lett., 99, 102903 (2011). [2] S. Fichtner, et al., J. Appl. Phys., 125, 114103 (2019). [3] C. Liu, et al., IEDM Tech. Dig. (2021). [4] S.-L. Tsai, et al., Jpn. J. Appl. Phys. 60, SBBA05 (2021). Figure 1

In recent years, HfO2 has been paid a lot of attention as a ferroelectric material due to its excellent scalability and complementary-metal-oxide-semiconductor (CMOS) process compatibility [1]. Some of the issues of ferroelectric HfO2 are wake-up and fatigue effect, increase and decrease of remanent polarization (P r) along with switching cycles, and low endurance. Generally, these phenomena are understood as a result of the increase and redistribution of oxygen vacancies (VO) in HfO2 films [2]. By the way, it is reported that CeOx can release and absorb oxygen from adjacent oxides [3]. In this study, we propose the stacking structure of CeOx and ferroelectric HfO2 to improve endurance and investigate electric properties and voltage application sequence to suppress the fatigue effect. 5 mol% Y-doped HfO2 (Y:HfO2) and CeOx capping layers of metal-ferroelectric-metal (MFM) capacitors were deposited by atomic-layer-deposition (ALD) with W bottom and top electrodes by sputtering. Post metallization annealing (PMA) was performed at 450 and 500oC for the various duration. Figure 1 shows hysteresis loops of the capacitors with and without CeOx capping annealed at 450oC for 20 minutes. Large hysteresis on CeOx capping is observed even same annealing temperature and duration. Enhancement of transformation to ferroelectric phase can be explained as tensile stress to Y:HfO2 due to the difference of coefficient of thermal expansion (CTE) between CeOx and Y:HfO2. Variation of switching polarization (P SW), the difference between positive and negative P r, as a function of the number of switching cycles is also investigated and shown in figure 2. Both capacitors are annealed at 500oC for 100 minutes to crystallize. In the case of without CeOx capping, continuous wake-up effect and breakdown over 3×107 times switching are observed. On the other hand, the capacitor with CeOx capping shows a slight wake-up effect and fatigue after 106 times switching, additionally, endurance is improved to 3×109 times switching. The reason why fatigue and prolonging endurance occur is suspected that oxygen ions in the CeOx layer pin polarization domains and compensate VO in Y:HfO2. To suppress fatigue, we propose the recovery process by positive DC voltage application to top electrodes. In figure 3, hysteresis loops of the capacitor with CeOx capping before and after recovery voltage application. One can observe the larger hysteresis after recovery. This work was supported by JST-COI (JPMJCE1309). One of the authors, Kazuto Mizutani, was supported by The FUTABA Foundation. [1] T. S. Boscke, et al., Appl. Phys. Lett., 99, 102903 (2011). [2] M. Pesic, et al., Adv. Funct. Mater., 26, pp. 4601–4612 (2016). [3] M. Mamatrishat, et al., Vacuum, 86, pp. 1513-1513 (2012). Figure 1

Herein we report on the positive Seebeck coefficient S = 162 μV K−1 of niobium (Nb)-doped MoS2 films prepared by sputtering and activation of Nb atoms by sulfur vapor annealing. The p-type doping achieved via these processes is discussed based on changes in chemical bonding states and resistivity behavior in terms of annealing and measurement temperatures. The results of this study provide a new option for p-type doping of MoS2 films and are expected to contribute to the development of nanoelectronics and a smart society.

A threshold voltage (V th) shifting method for GaN high electron mobility transistors using self-upward polarized Al1-x Sc x N gate dielectrics was proposed. The direction of the spontaneous polarization was controlled by the insertion of an Al2O3 layer between the Al1-x Sc x N and the AlGaN layers. A V th shift of 8 V was found by changing the direction of the polarization. The thickness scaling in the Al1-x Sc x N layer from 40 to 30 nm showed a linear relationship to the V th, revealing to retain a high spontaneous polarization. A high positive V th for enhancement-mode (E-mode) operation is feasible with the method in combination with a recess process.

The effects of field cycling of Al0.78Sc0.22N capacitors on ferroelectric properties are investigated. In the first hundreds of switching cycles, the reduction in the switching voltage was observed, possibly due to the formation of nitrogen-vacancy to facilitate the atom displacements. With further switching cycles, fatigue effect was observed, especially for domains with low switching voltage. The leakage current analysis indicates continuous downward band bending with the number of switching cycles, effectively reducing the Schottky barrier height for electrons. The breakdown of Al0.78Sc0.22N films is triggered by the Joule heat due to excessive leakage current. The mechanism is in contrast to conventional ferroelectric materials, where the breakdown is triggered by Joule heat at the local conductive filaments.

Silicon trench-gate insulated gate bipolar transistors (IGBTs) were analyzed using technology CAD (TCAD). Excellent agreement was confirmed between the $J_{\mathrm{C}^{-}}V_{\text{CE}}$ characteristics obtained by 3D- TCAD simulations and experiments. The carrier lifetime requirement for scaled trench-gate IGBTs was determined by extraction of the on-resistance of the n-base layer derived from the electric potential profile.

WS 2 pMISFETs are successfully demonstrated by radio-frequency magnetron sputtering and sulfur-vapor annealing with TiN/HfO 2 -top-gate-stack, TiN contact and ultra-thin body and box (UTBB). The WS 2 film with (002) plane was formed in parallel to a substrate surface. I-V characteristics with p-type operation are confirmed with the maximum field effect mobility of 0.69 cm2V−1s−1. This WS 2 film is expected for not only the CMOS circuits but also thermoelectric generators.

ZrS2 amibipolar MISFETs are obtained in operations with both electrons and holes. A layered polycrystalline ZrS2 thin film was formed by sputtering and sulfur-vapor annealing on a whole surface of a 2.4 cm × 2.4 cm SiO2/Si substrate. The ZrS2 FETs have Al2O3 gate insulator and TiN film for both the top-gate electrode and Schottky-barrier contact, which show symmetrical I d–V gs curves with a V off of 0.4 V contributed by the TiN film with midgap work function to the sputtered ZrS2 film. Notably, ambipolar FET operations because of both electrons and holes were successfully observed with an on/off current ratio of 250. This is an important step to realize n/p-type unipolar ZrS2 FETs.

Full integration of a back-gate-controlled IGBT (BC-IGBT), which comprises top and bottom independently controlled MOS gates, is experimentally demonstrated. By using the back side MOS gate for accelerating electron drain and blocking of hole injection, more than 60% reduction of turn-off loss was achieved. Instead of the conventional wafer bonding approach, a cost effective process flow using double side lithography has been developed and used. Thanks to the process flexibility, back side design was carefully optimized to achieve stable operation and manufacturability, in addition to low switching loss. BC-IGBT will provide a new technological option for expanding the applicable switching frequency / voltage range of Si power devices.

The sputtering power dependence of 40 nm thick Al0.7Sc0.3N ferroelectric properties was characterized from 200 to 300 W. X-ray rocking curve revealed higher orientated growth into the c-axis with higher sputtering power. Films formed by high power showed reduced leakage current with a higher breakdown field, enabling one to apply the high field for ferroelectric switching. A high remnant polarization (P r) of 130 μC cm−2 was obtained with a coercive field (E c) of 6 MV cm−1. The switching cycle test revealed a wake-up effect for all the films; increasing the leakage current and modifying the E c. We anticipate the change is attributed to the existence and the generation of nitrogen vacancies (V N) in the films.

Technology CAD (TCAD) has been recognized as a powerful design tool for Si insulated gate bipolar transistors (IGBTs). Here, physical models, such as a mobility model for carrier-carrier scattering, were investigated for a predictive TCAD. Simulated currentvoltage characteristics of the trench-gate IGBTs were compared with measurements. The difference between 3D- and 2D-TCAD simulations was observed in a high current region, which was explained by a bias-dependent current flow. A test element group (TEG) for separation of the emitter currents for holes and electrons was also determined as effective for calibration of lifetime model parameters.

The impact of annealing temperature and the duration on the dielectric properties of atomic-layer-deposited (ALD) 5 mol% Y-doped HfO 2 capacitors have been examined. Besides the ferroelectric behavior of the capacitor over an annealing temperature of $500^{\circ}\mathrm{C}$ for short period, the appearance of ferroelectricity has been obtained at $400^{\circ}\mathrm{C}$ when annealed over 5 min. A fairly nice ferroelectric property with a remanent polarization P r of 12 $\mu$/cm2 after wake-up process has been obtained.

A novel BEOL compatible three-layered structure based on ferroelectric (FE) HfO 2 device is proposed for endurance improvement. This structure consists of an ultrathin Y 2 O 3 passivation layer, a FE Y-doped HfO 2 layer (YHO, deposited at room temperature (RT)) and a buffer CeOx layer. Y 2 O 3 is used for passivation of defects with the bottom electrode (NiSi 2 ) while CeOx is used to control oxygen vacancies in FE-YHO. Good FE hysteresis is observed in YHO (from 12.5 to 9.2 nm) while low temperature activation annealing (200°C-400°C after CeOx deposition), greatly enhances the FE-YHO properties. After annealing at 350□, this novel capacitor (YHO= 9.2nm) shows lower leakage current, initial remanent polarization of 25μC/cm2 (2Pr), excellent endurance up to 1e12 cycles at low power operation conditions and good data retention at RT.

Sputtering enables uniform and clean deposition over a large area, which is an issue with exfoliation and chemical vapor deposition methods. On the other hand, the process of physical vapor deposition (PVD) film formation has not yet been clarified. We prepared several samples from the sub-monolayer region, and performed Raman spectroscopy, X-ray photon spectroscopy and high-angle annular dark-field scanning transmission electron microscopy. From these results, the internal stresses inherent to PVD films, the bonding states specific to sub-monolayers, and the unique film structure and the grain formation process of PVD films were discussed from the perspective of sub-monolayers. As a conclusion, we found that it is important to suppress the formation of sub-monolayers on the substrate to completely form the first layer.

A high Seebeck coefficient of 1.17 × 103 μV K−1 was achieved using an on-chip thermoelectric device for a WS2 atomic-layer film, which was synthesized by ultra-high vacuum RF magnetron sputtering as a function of sputtering power. A layered structure in parallel to the SiO2/Si substrate was confirmed from the transmission electron microscopy and X-ray diffraction spectra. The grain size and peak intensities of the Raman spectra increase with a decrease in the sputtering power. Accordingly, the resistivity and activation energy also increase. The WS2 film can be used in thermoelectric generators, such as energy harvesters in LSIs and wearable devices.

In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage (V dd ), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2. A hybrid self-assembled monolayer/aluminum oxide (AlO x ) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping technique and gate stack technology, we experimentally realized a high gain of 9 at V dd of 0.5 V in the WSe2 CMOS inverter. This study paves the way for the research and development of transition metal dichalcogenides-based devices and circuits.

The effects of 1 nm thick CeO x capping on 7.5 nm thick Y-doped HfO2 films on the ferroelectric characteristics are investigated. From the ferroelectric characteristics of the samples annealed at different temperatures from 450 °C to 600 °C and annealing durations, the time (τ) required to stabilize the ferroelectric phase at each temperature was shortened by the capping. The identical activation energy (E a) of 2.65 eV for ferroelectric stabilization without and with capping suggests the same kinetics for phase transformation. However, an increase in the remnant polarization (P r) was obtained. Only a few Ce atoms diffused into the underlying HfO2 film even after 600 °C annealing. Ferroelectric switching tests revealed an improvement in endurance from 107 to 1010 by the capping, presumably owing to the suppression of conductive filament formation. Therefore, CeO x capping is effective in promoting the ferroelectric phase in HfO2 with high switching endurance.

In this paper, we investigated the source/drain recessed contact structure to mitigate the self-heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of nanowire regions during device operation was considerably decreased by using the source/drain recessed contact structure. This is attributed to an increase in heat dissipation mainly from heat source to bulk wafer. Moreover, we proposed the p/n-stacked nanowire on bulk FinFET and its 6T-SRAM layout. Area of the proposed SRAM was reduced approximately 15%, as compared to the conventional cell layout.

The inconsistency of symmetry relationships in nonlinear piezoresistance coefficients, which is a long-standing puzzle, is resolved by taking into account the complex relations between piezoresistance coefficients and piezoconductance coefficients. The procedure to obtain correct nonlinear piezoresistance coefficients in theory according to the coordinate transformations of tensors is suggested.