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In this letter, we have demonstrated a packaging technique for 3-D IC with Cu back-end-of-the line (BEOL) on a mixed pitch (55 and $75~\mu \text{m}$ ) advanced ground-rule laminate by developing a 3-D die-stack on substrate (3D-DSS) technology. 3-D DSS is a new assembly technology to address issues caused by warpage and mechanical stress response of 3-D integration packaging when bonding a thin through-silicon via (TSV) die on an organic substrate. The $35\,\,\text {mm} \times 35$ mm test substrate has high density interconnects which include four wiring layers with thin film insulators on the chip mounting side of conventional buildup layers. A minimum 2 $\mu \text{m}$ /2 $\mu \text{m}$ line/space is constructed on this advanced ground-rule laminate. The experimental results showed that the 3-D DSS method can effectively prevent microbump opens or shorts, and can produce good solder joints between thin TSV die in a 3-D configuration on a fine, mixed pitch laminate.

Handwriting was since the start of the history, a higher expression of human skills, and was used for documentation of experiences, and for communication. Existing writing technology require a writing tool, like a pen, and a dedicated writing surface, like paper, or more recently an electronic tablet. These accessories of writing, of writing tool and service, are not available in many daily life situations. Furthermore, the writing accessories, are not natural, in many cases are not ergonomic, and thus can cause fatigue, and in extreme cases contribute to muscular and neurological diseases. In this work, we suggest to step back in history and step forward in technology, and to create, for the first time, an alternate writing solution without any accessories, using one own finger as writing tool, and write on almost any surface. For this, we used directional pressure sensors attached to the fingernail. Changes in the pressure induced on the fingertip in different directions while writing, are projected to the fingernail, and then assessed as a voltage pattern by the sensor. Decoding the pattern, can reveal symbols like letters, punctuations, and writing commands. In this paper, we describe the new pressure sensing modality and tailor processing methods. We tested the new technology on two subjects having different writing patterns while writing alphabet and sentences on different surfaces. We reached letter detection of over 80% while writing on a table, and the word detection rate, was near 70%, after applying the correction algorithm include language priors. The results of this work can revolutionize the way people write and communicate using more convenient, and more approachable, finger-tip writing.

Wearable sensors can provide important human physiology and activity data and therefore have promising applications in healthcare, entertainment, and security. Here, we report the design, fabrication, and characterizations of a thin silicon film sensor for wearable sensor applications. Temperature, light, and strain sensing capabilities of the thin film of doped silicon, fabricated using a controlled spalling process, were fully characterized. An n-doped silicon thin-film sensor prepared with the spalling technology exhibited a temperature coefficient of −0.44%/°C. The sensor also showed excellent light sensing response in an illumination range from 110 to 1710 cd/mm2. The ratio of the electrical resistance changes over the applied forces was measured to be around 0.6%/N.

In this work, a 3D Die-Stack on Substrate (3D-DSS) bonding process has been developed to demonstrate a 3D die stack that has been joined to a mixed pitch ( $5\ \mu\mathrm{m}\ /\ 75\ \mu \mathrm{m}$ ) high density interconnect laminate. By using the 3D-DSS process with thermal compression bonding, the thin bottom die with the TSVs can be bonded to a thick top die by being held flat with a silicon vacuum stage. This study used a semiconductor die that consisted of mixed pitch ( $55\ \mu\mathrm{m}\ /\ 75\ \mu \mathrm{m}$ ) Cu pillars with a SnAg solder cap. The dimension of the high-density laminate was $35 \text{mm} \times 35\ \text{mm}$ and it had thin film high density layers on standard build up layer. The thin film layers are directly integrated to one side of a conventional substrate. A major challenge for this technology lies in the interconnection reliability. To address that, sub-modeling of the interconnects was performed. The stresses in the solder micro-bump, back-end-of-the-line (BEOL) and the vias in the wiring level is presented. A selective cross-sectional analysis was used to study the geometry of the micro-bump connections after forming the 3D die stack on the advanced ground rule laminate. The analysis confirmed that mixed pitch solder joints along the perimeter of chips were joined with full wetting and no bridging.

In this paper, we have demonstrated a plasma activated low-temperature die-level oxide-oxide direct bonding with advanced wafer dicing technologies. This evaluation used blanket 300-mm silicon wafers. $1\ \mu\mathrm{m}$ Tetraethyl orthosilicate (TEOS) oxide was deposited by plasma-enhanced chemical vapor deposition (PECVD) directly on the silicon (Si) wafer surface, followed by chemical mechanical planarization (CMP). Atomic Force Microscopy (AFM) was used to examine the roughness of the wafer surface before dicing and it showed $\mathrm{R}_{\mathrm{a}}$ . Several dicing technologies such as diamond blade dicing, step-cut blade dicing, bevel blade dicing, and stealth laser dicing were evaluated for this integration scheme. In the end, diamond blade dicing has the most compatibility with many materials, but it led to large chipping on the edges of the die. Stealth laser dicing achieves edge chipping of less than $2\ \mu\mathrm{m}$ , which is the least amount of damage among of all dicing methods tested in this study. In the bonding test, the 10 mm square silicon die was bonded to a 35-mm square silicon substrate. Both silicon die and substrate are of thickness $760\ \mu\mathrm{m}$ . Prior to direct oxide-oxide bonding, both silicon die, and substrate went through a two-step cleaning process. The detailed process of the plasma activated die-level direct bonding is discussed.

Wearable electronics are demanded in many applications. However, traditional semiconductor manufacturing is based on bulk wafers and it is very challenging to mass-producing flexible electronics. In the last decades, many technologies have been developed to address this challenge such as using flexible materials instead of silicon, using silicon on insulator surface and peeling off the top thin silicon films. Here, we review another promising technology for achieving flexible electronics – controlled spalling, which uses mechanical stress to facilitate peeling off thin film directly off a bulk silicon substrate. This technology is CMOS-compatible (where CMOS is complementary metal-oxide-semiconductor) and can potentially achieve system-level wearable electronics integrating sensors, signal processing, and communicating units.

The dynamics of the human fingertip enable haptic sensing and the ability to manipulate objects in the environment. Here we describe a wearable strain sensor, associated electronics, and software to detect and interpret the kinematics of deformation in human fingernails. Differential forces exerted by fingertip pulp, rugged connections to the musculoskeletal system and physical contact with the free edge of the nail plate itself cause fingernail deformation. We quantify nail warpage on the order of microns in the longitudinal and lateral axes with a set of strain gauges attached to the nail. The wearable device transmits raw deformation data to an off-finger device for interpretation. Simple motions, gestures, finger-writing, grip strength, and activation time, as well as more complex idioms consisting of multiple grips, are identified and quantified. We demonstrate the use of this technology as a human-computer interface, clinical feature generator, and means to characterize workplace tasks.

This paper describes the sensor, electronics, software, modeling, and characterization of a fingernail-mounted RF-connected wearable strain sensor system that measures nail deformation from finger movement. Applications to health monitoring and human computer interfaces in homes, hospitals, and workplaces are discussed. The mechanical deformation of a fingertip pressed or drawn against a plate is demonstrated using a three-dimensional finite-element linear-elastic model to predict the signal level, optimum sensor locations and the type and location of deformation expected for different finger motions. The 3D finite-element linear elastic model is derived from X-ray images of a human finger but generalized and parameterized to allow new models to be created by scaling internal and external parameters such as skin thickness and nail and finger shape to predict sensor system performance for a more general human population. Our analysis finds that a single sensor mounted in the center of the nail will respond to typical grip pressures on the fingertip with readily detectible strain amplitudes but that a multi-sensor array will be sensitive to more general haptic phenomena such as the direction and magnitude of frictional loads and loading of the distal phalangeal joint. It is shown that depending on finger use and loading the nail exhibits shifts in direction, location and sign of strain over the fingernail surface. Measurement data from a simple multi-sensor array is shown to be useful in distinguishing between load conditions, however additional sensors are required for full determination.

In this research study, we present comprehensive characterizations of flexible silicon sensors fabricated using controlled spalling which uses fracture to produce thin films of single-crystal silicon directly from a bulk substrate. We characterized the property of the thin silicon film for sensing strain and temperature. The flexible sensor exhibits high sensitivity with a temperature coefficient of resistance of −0.16/°C, which is desirable for targeted health monitoring applications.

Innovations in healthcare, diagnostics, sensors and data analysis with Artificial Intelligence (AI) learning / recommendations offer opportunities for improved personalized healthcare, lower costs and benefits to the medical industry. The age of personalized human health monitoring has begun. Human health monitoring using fluidic diagnostic monitoring, non-invasive sensors, wearables (electronic health sensors), implanted health sensors, sound, visual images, and combinations of these data trends offer individuals personalized healthcare guidance. The data, analytics and recommendations from these personalized solutions are beginning to aide our early detection and understanding of health risks from chronic diseases and overall health / wellness. Examples include: cardiovascular disease, diabetes, oncology / cancer, kidney disease, elder care, Parkinson / Huntington Diseases, and many other healthcare applications. Rapid advancements of innovative healthcare diagnostic tools, health and environmental sensors along with data trending and analysis using AI systems or platforms can provide industry disruptions in healthcare. AI systems already aid health professionals and individuals with knowledge and recommendations that offer the promise of improved quality of life and lower healthcare costs. Examples such as: (1) earlier chronic disease detection and potential for disease progression delay or prevention, (2) understanding individual behavior, medication treatments and effectiveness of the treatments on activities of daily living and (3) personalized care based on your DNA, medical diagnostics and your healthcare trends relative to your healthcare needs and options to manage your quality of life. In this paper, we describe both new technologies and advancements to heterogeneous integration technology tools, materials and processes that provide differentiating electronics for future healthcare diagnostic tools and sensors. These new technologies are being applied to targeted applications in healthcare diagnostics and sensor monitoring for precision diagnostic data, smaller product size and much lower costs. Data streams can leverage AI to provide smart personalized healthcare guidance or solutions that compliment existing technology and data to partners such as healthcare professionals, patients and clients. In many applications, we leverage industry available technology or benefit from these new technology advancements to provide for the best system solution. Examples of these new and advancing technologies include: (1) Precision handling thinned wafers with large die, small die, multi-die, sub-components, components and substrates technologies, (2) Injection molded solder (IMS) technology for wafers (TSV and / or interconnection) and substrates, (3) Precision micro-component, die, multi-die substrate and multi-component assembly / integration technology for healthcare, IoT and AI Systems, (4) Precision laser micro-machining, cutting and welding technology, (5) Flexible multi-channel, micro-fluidic systems for smart sensing, point of care (POC) diagnostics, and AI and (6) Small form factor micro-systems and energy solutions / technologies that support future healthcare, IoT, and AI linked computing solutions. Examples of key challenges and advantages of these technologies for the targeted applications are shared relative to current industry standard solutions. Highlights on future demonstrations in progress at the time of writing this paper are targeted for our 2018 ECTC presentation and other future technical publications.

Tin alloys are widely used as solder for electronic interconnections. Tin solder surfaces tend to have tin oxides which need to be removed to improve the yield of interconnection reflow processes such as flip chip joining. Conventionally, a strong flux is employed to remove these oxides, however this process has the drawbacks of leaving flux residue which can cause underfill delamination or require a high-cost cleaning process. As solder bump volumes and bump-to-bump spacing decrease, these problems become more difficult to manage in manufacturing. We propose the use of Atmospheric Plasma to reduce these oxides from the bump surfaces to enable the use of very light fluxes, or no flux at all. This process has the advantages of plasma surface preparation without the cost and throughput penalty of vacuum plasma processes. Such a process can increase throughput and yield while reducing the cost. We describe an experiment in which tin foils were treated with a reducing-chemistry Atmospheric Plasma process and then analyzed with X-ray photoelectron spectroscopy (XPS) and Auger Electron Spectroscopy (AES). AES depth profile analyses indicate that the thickness of tin oxides was significantly reduced by the plasma. There was no evidence for any etching of underlying elemental tin. These results suggest that tin oxides are reduced to metallic tin without etching of the underlying tin metal. In another similar experiment using semiconductor chips with SnAg solders, XPS results suggest that the tin oxides were again reduced to metallic tin. In flip chip joining, the joining process with such Atmospheric Plasma-treated chips achieved high interconnect yield, even in the case of poor quality solder balls with excessive oxidation. It is our understanding that the pure chemical reduction of tin oxides with atmospheric plasma in ambient had not been previously reported.

3D multi-layer chip stacking is a significant assembly challenge with dependencies on die size and thickness, interconnect pitch, bump diameter, number of dies involved, and die warpage. The assembly processes used to overcome the technical difficulties associated with the stacking of medium and large logic dies with fine pitch copper pillar bumps is discussed, including mass reflow and thermo-compression bonding on 3 and 4 layers chip stacks.

In this paper, we describe a hybrid bonding technology of Au microbump and adhesive using a planar adhesive structure for 3-D large-scale integration (LSI). Hybrid bonding means that both the microbump electrode and adhesive are simultaneously bonded. In 3-D LSI, the gaps between bonded chips are ${ because the pitch of the microbumps is decreased. Conventionally, adhesive resin is injected into the gaps by means of capillary force. However, the filling of the gaps is insufficient due to surface conditions. To address this challenge, we evaluated hybrid bonding with a planar adhesive structure fabricated by chemical–mechanical polishing. The bonding results showed that connection between the Au bumps and adhesive filling in the 6- $\mu{\rm m}$ gap between bonded Si chips was achieved without readily visible void in the range of 6 mm $\times\,$ 6 mm. All 900 bumps were also electrically connected. The shear strength of the bonded sample was 13 MPa. Therefore, we determined that the proposed hybrid bonding technology is highly effective for 3-D LSI with fine-pitch microbumps.

This paper describes a hybrid Au-underfill resin bonding method with lock-and-key structure for 3-D integration. In 3-D large scale integration (LSI), the gap between stacked chips becomes narrower because the bump dimension and pitch are smaller than those encountered in 2-D LSI. Therefore, the filling of gaps less than 10 μm using capillary forces often becomes insufficient because of the surface condition. To address this challenge, we study a hybrid bonding method in which the metal-metal and resin-resin bonding are carried out simultaneously with a chip resin applied previously only around the bump. To realize hybrid bonding on the entire chip, we fabricate indent and protrusion structures, which are called lock-and-key structures. The key structure is fabricated by a process that can remove the resin on the bumps by O2 plasma irradiation. The lock structure is fabricated by conventional photolithography and dry etching. By means of hybrid bonding with the lock-and-key structure, we have achieved the Au bump bonding and the filling of 4-μm gaps between the stacked chips, concurrently. The cross-sectional transmission electron microscopy image of the bonded sample demonstrated that no significant gap exists at both the Au-Au and resin-resin interfaces. In addition, the shear strength of the sample bonded with resin is 10 times higher than that without the resin. The electrical continuity of the Au bump connections after hybrid bonding has also been determined.

Low-temperature Au­Au bonding was achieved under vacuum ultraviolet irradiation in the presence of oxygen gas (VUV/O3). The Au surfaces obtained after the VUV/O3 treatment were analyzed by X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM) measurements. The results indicate that the amount of carbon-based contaminants was dramatically decreased and that there was no serious damage to Au surfaces caused by the VUV/O3 treatment. The Au­Au bonding temperature was successfully reduced to 150°C after the VUV/ O3 treatment. The average shear strength was approximately 56MPa, and cross-sectional scanning electron microscopy (SEM) images of the bonded samples confirmed the absence of voids and cracks. Therefore, VUV/O3 treatment is highly effective for achieving low-temperature Au­Au bonding. [doi:10.2320/matertrans.MF201313]

Over the past decades, the downscaling of transistor dimensions has improved circuit performance, power, and integration density. However, conventional device scaling is approaching the physical limits and it is increasingly difficult to sustain the same miniaturization scaling rate. Three-dimensional (3D) integrated circuits that stack multiple functional chips using through-silicon-vias (TSVs) and low-volume lead-free solder interconnects may overcome these problems, because this approach makes it possible to reduce global interconnect length and to increase device density without shrinking device dimensions. Different levels of 3D integration investigation were previously reported and updated. The current paper reviews the 3D integration technologies, including process technology and reliability characterization.

This paper focuses on the effects of a vacuum ultraviolet (VUV) surface treatment process on the interconnections for flip chip and 3-D integration. Organic contaminants that hinder reliable bonding are broken down and eliminated from the bumps and pad surfaces by irradiation with UV light at a wavelength of 172 nm at room temperature. There is no charge buildup, no temperature increase, and no ion bombardment damage during the process. Two different VUV cleaning conditions, with N2 or O2 gas in the vacuum chamber, were compared and evaluated. Samples of flip chip with Cu/Sn bumps and Au surface substrate were examined by measurement of contact angle, X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM), and atomic force microscopy (AFM) before and after VUV surface treatment. Cleaning times and ambient conditions have dramatic effects on the surface contact angles. The photoelectron spectra of C 1s were obtained by XPS analysis for information on the chemical species and the XPS results showed a reduction in surface carbon for both Au and Cu/Sn after the cleaning. The evidence indicates cleavage of the carbon-carbon bonds in the organic molecules occurs during the cleaning process. From the shear test results, it appears that VUV treatment improves the Cu/Sn-bump bonding strength, making it two times larger than for untreated samples. No delamination or obvious voids were detected on the bonding interface by Scanning acoustic microscopy (SAM) and cross-sectional SEM analysis. The experiments show that the VUV cleaning can effectively remove the organic contaminants on the surface of the bonding pads and improve the bonding strength.

Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (

Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.

Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.

A Design of Experiments (DOEs) matrix was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Based on measured samples, functionality test and leakage test show circuit performance degradation and larger fail rate after chip bonding on designs without ESD protection.

In this work, a controlled thermo-compression (TC) bonding process has been developed to address problems caused by interposer and laminate warpage when assembling large three-dimensional (3D) integrated circuit (IC) die on an organic substrate (laminate). By using TC bonding, a thin interposer with through-silicon-vias (TSV) is joined to a top die while being held flat by vacuum and vertical pressure. A vacuum distribution plate is developed and used to mitigate warpage during 3D assembly. A unique set of process parameters has been developed which enables the joining of severely bowed, large area interposers to a semiconductor die without C4 (Controlled Collapse Chip Connection) shorting. The controlled TC bonding method developed in this work offers a huge advantage when joining multiple large warped die in a stack. This evaluation used a large 22 nm CMOS top die with ultra low-K (ULK) back end of the line (BEOL) and copper pillar/SnAg solder bumps at two different pitch sizes, 61 µm and 131 µm. Both the top die and interposer die were larger than 600 mm2 while the organic substrate was 68.5 mm × 68.5 mm. The top die and interposer were bonded with parameters developed for an enhanced TC bonding process. Cross-sectional analysis of the 3D assembly showed that the solder joints along the perimeter of chips exhibited good joining with good solder wettability and no solder bridging. Non-destructive X-ray analysis also confirmed that there were no C4 bump bridging across the entire chip area. The experimental results verified that the enhanced TC bonding process can effectively prevent C4 bump bridging and C4 bump electrical opens for a large die packaged in a 3D configuration with a highly warped large area silicon interposer.

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm 2 . Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.