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In order to address the Chip-Package Interaction (CPI) risks associated with advanced silicon packaging, GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in the Backend of Line (BEoL) and Far Back End of Line (FBEoL) during the flip-chip assembly process and multiple reflow (MR) cycling test. This paper discusses the complexity involved in the CPI mechanical performance and use of various modeling methods to assess and mitigate the CPI failure risk. The paper also highlights the quantitative package model validation against experimental data based on newly developed Cohesive Zone Material (CZM) modeling methodology.

In order to address the Chip-Package Interaction (CPI) risks associated with the Wafer Level Chip Scale Package (WLCSP), GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in the Backend of Line (BEoL) and Far Back End of Line (FBEoL) during mass reflow process. This paper discusses the CPI failure risk associated with WLCSP, modeled with and without the redistribution layers (RDL) introduction above the BEoL. The WLCSP model has been modified to assess the design variations within the RDL and the FBEoL. The paper also highlights the FE model verification between the two-dimensional (2D) versus the three-dimensional (3D) models and validation by comparing the simulation results to the experimental test data.

This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow. Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.

This paper describes a systematic approach to the identification of primary contributing factors to the Chip Package Interaction (CPI) risk and reveals the mitigation strategy successfully applied by GLOBALFOUNDRIES. The strategy includes modeling at bump and package level, gathering experimental data on blanket dielectric back end of line (BEoL) films, collecting data on wafer material with a complete BEoL stack, and finally using readouts on the package level. Advanced measurement methods generate data on the wafer level to achieve fast turn-around times. These methods include: (i) Dual-Cantilever Beam (DCB) test, (ii) Modified Edge Lift-off Test (MELT), (iii) Single Pillar Shear Test (SPST) and (iv) Bump Assisted BEoL Stability Indentation (BABSI) tests. The paper describes the methodology to gather data on the wafer level with a complete BEoL metallization stack that assesses the BEoL integrity. Furthermore, the package level thermomechanical modeling approach is discussed. The model has been used to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow processes. Silicon design-related factors in the BEoL that contribute to the risk for CPI related failures were investigated and options to reduce the CPI risk are discussed. Finally the paper reveals package level qualification data flip-chip CSP and wafer level packaging Fan-In for advanced technology nodes.

With the recent increase in Gold (Au) wire cost; Copper (Cu) wire becomes an attractive way to manage overall package cost. On the other hand, Copper wire bonding introduces much higher mechanical impact to underlying BEoLstructures and actives because of the higher stiffness and lower ductility of Copper compared to Gold. These trends are accompanied by the application of new porous or nano-particle filled materials like low-k and ultra low-k materials for Back-end of line (BEoL) layers of advanced CMOS technologies. As a result, higher delamination and cracking risks in BEoLstructures underneath bonded areas represent an increasing challenge for the thermo-mechanical reliability requirements. To overcome the related reliability issues the authors performed a two level nonlinear FEM-simulation approach. Initially nonlinear axisymmetric modeling and simulation of the copper bonding process are coupled with a spatial simulation model of the whole BeoL and bond pad structure. Cracking and delamination risks are estimated by a surface based cohesive contact approach and the utilization of a crushing foam constitutive material model for ultra low-k materials.

In order to address the Chip-Package Interaction (CPI) challenges at an early stage of the product development, GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in Backend of Line (BEoL). This paper elaborates the methodology involved in developing a single bump simulation model to assess failure risk under mechanical loading. The paper also highlights the FE models validation by comparing the simulation results to the experimental test data.

The introduction of fragile ultralow-k materials as interlayer dielectrics in backend-of-line interconnect stacks asks for a thorough analysis of potential risks due to chip-package interaction. This paper shows how the application of several ex-situ and in-situ experimental approaches can be effectively used to assess such risks on the wafer level already at early stages of the development phase. The respective analytical techniques try to mimic chip-package interaction loading conditions. Most of the tests transfer loads to interconnect stacks via individual copper pillars. The investigations take place on the scale of about 100μm down to 1μm.

Package-induced failures for BEOL interconnects in sub-45nm technology nodes have drawn attention to the great silicon and packaging integration challenges introduced by the weak mechanical properties of ULK-containing metallization elements. Empirical data and modeling studies for a range of silicon and packaging factors at 20nm node reveal fundamental insights into susceptibility to damage and approaches for recovery. Analysis of increase in degradation as BEOL layouts evolve to finer dimensions points to understanding of changes that will enable continued device scaling.

Fhis paper discusses the extensive development work carried out by GLOBALFOUNDRIES to mitigate chip-package interaction (CPI) risks for the silicon Backend of Line (BEOL) during IC package assembly. Particularly, material property data for different ultra low k (ULK) materials, CPI qualification results and key findings made during the technology development are discussed. Newly developed test and modeling methods to expedite technology learning are also described in detail.

Chip-package interaction has become a major concern due to increasingly porous low-K dielectrics. During the packaging process, shear stresses are exerted on fragile interconnect structures. We use a microprobe metrology system to experimentally measure how interconnect stacks with different dielectric porosities behave under various shear loading conditions and a wide range of temperatures. © 2012 IEEE.

We address package-induced degradation of BEOL interconnects and approaches for recovery. For dielectrics, we cover process options and position in stack for ULK films and how these lead to differences in strength. Experiments were designed to cross-compare multiple methods to test susceptibility of BEOL interconnect to CPI damage. We also address how Chip Package Interaction changes as BEOL features and layout evolve.