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Chip Package Interaction (CPI) risk assessment of 22FDX® Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling

Authors :
Kristina Young-Fisher
Dirk Breuer
Frank Kuechenmeister
Jae Kyu Cho
Kashi Vishwanath Machani
Christian Klewer
Source :
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
Publication Year :
2020
Publisher :
IEEE, 2020.

Abstract

In order to address the Chip-Package Interaction (CPI) risks associated with the Wafer Level Chip Scale Package (WLCSP), GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in the Backend of Line (BEoL) and Far Back End of Line (FBEoL) during mass reflow process. This paper discusses the CPI failure risk associated with WLCSP, modeled with and without the redistribution layers (RDL) introduction above the BEoL. The WLCSP model has been modified to assess the design variations within the RDL and the FBEoL. The paper also highlights the FE model verification between the two-dimensional (2D) versus the three-dimensional (3D) models and validation by comparing the simulation results to the experimental test data.

Details

Database :
OpenAIRE
Journal :
2020 IEEE 70th Electronic Components and Technology Conference (ECTC)
Accession number :
edsair.doi...........fb8c3f82ef5d735aeb244b20f416fca9
Full Text :
https://doi.org/10.1109/ectc32862.2020.00177