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As the industry continues to push the limits of integrated circuit fabrication, reliance on EUV lithography has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at Litho and Etch together with eliminating film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns. In particular improvements in the coater/developer hardware and process are required to enable the use of a wide variety of chemicals as well as compatibility with existing systems. This paper reviews the ongoing progress in coater/developer processes that are required to enable EUV patterning sub-30nm line and space by using MOR (Metal Oxide Resist).

Comprehensive EUV resist characterization for line and space patterns at pitches between 32 and 40 nm using scatterometry in conjunction with machine learning algorithms is presented and discussed. Controlled experimental variations of EUV single expose resist lines were introduced by exposure dose and illumination conditions. Scanning electron microscopy and atomic force microscopy were used to collect reference data. The developed machine learning solutions allow for determination of four characteristic resist metrics with a single scatterometry measurement: line width, line height, line edge roughness, and line top roughness. Therefore, in excellent agreement with reference metrology, the scatterometry measurement, can replace four individual operations for rapid and accurate in-line monitoring.

As the semiconductor industry continues pushing Moore’s law to the next node, interconnect structures scaling will be a key element to performance improvement of functional devices. However, the requirements for low LCDU and defectivity of these interconnect structures have become more stringent with continuous scaling. In this paper, a fundamental study is conducted to understand the impact of various factors on the patterning of EUV single exposure vias, and to find effective strategies to shrink CD while improving LCDU and defectivity. The work is based on a 40 nm pitch orthogonal via array baseline, and probes different patterning factors including illumination, resist materials, stack, scanner, and develop methods for LCDU improvement and defectivity reduction. The patterns are transferred to bottom dielectrics to study the evolution of LCDU and defectivity during etching.

In 2015 IBM announced the first 7 nm test chip patterned with Extreme Ultraviolet Lithography (EUV) technology, enabling 36nm back end of the line (BEOL) metal pitch and self-aligned contact. Five years later, EUV has become the mainstream enabler for 7 nm node manufacturing, including the recent announcement of IBM Power10 high-performance chip. The high-performance definition of this technology, essential to IBMs server chips, has unique requirements that push the process complexity even further. In this paper, we will review some of the challenges and patterning solutions that will allow successful implementation of high-performance design definitions. We will also discuss our current efforts to extend the use of single expose EUV in the printing of interconnects to a second node, over a multi-patterning scheme, by replicating our strategy of co-optimization across all contributors to patterning success. We will review a few examples of this approach, including resolution improvements of our latest NXE3400 EUV system, all of which have allowed us to realize significant yields for our transistor interconnects at 28nm pitch. The entitlement of each process and material will be gauged through a robust characterization methodology that includes an understanding of the defect mode modulated, as well its ultimate correlation to electrical yield.

As future patterning processes reach the limit of lithographic printability, continuous innovation in mandrel trim or shrink strategies are required to reach sub-20 nm line-space patterning. Growing concerns of lithography defectivity, mask selectivity, line edge roughness (LER), line width roughness (LWR), and critical dimension uniformity (CDU) present significant challenges towards this goal. The authors compare various alternative mandrel trim strategies to highlight potential solutions and drawbacks towards enabling successful printing of mandrels used in extreme ultraviolet (EUV) multi-patterning schemes. Through this comparison, the authors demonstrate the challenges of maintaining adequate pattern transferability while keeping aspect ratio-driven line roughness and material selectivity under control. By process partitioning, the limitations of traditional lithography and etch trimming strategies are highlighted, suggesting the need for new methods of CD reduction after the pattern has been transferred. These new trimming methods offer flexibility in CD control without negatively impacting the mandrel profile and demonstrates better tunability across different material sets, allowing for evaluation of different mask and mandrel material combinations for downstream process optimization.

Emerging memory devices, such as MRAM, RRAM, and PCM, plays an important role in in-memory computation technology which can lead to significant acceleration for machine learning and AI applications.[1-3] The basic structure of these memory cell is simply a pillar made of a wide range of materials, however, the local CD uniformity (LCDU) of the pillars is especially crucial for these memory devices. The stringent LCDU requirement derives from either the intrinsic small resistance difference between the two memory states or the requirement for creating a large number of memory states within a small range of resistance. Apparently, the stochastic variation in physical dimension will correspond to the variation in resistance from cell to cell, which will affect the correct readout of the memory states and fail the device. Because the “local” CDU in this context refers to the variation within the memory array, i.e. typically within several um, it is almost impossible to correct by utilizing existing advanced tools or process control techniques. In this work, we will demonstrate four promising options to address the stochastic effect in LCDU of pillars: a) adopting new resists, b) PTD and NTD shrink, c) DSA, d) cross-SADP. Fig. 1 shows the general approach to achieve better LCDU by printing larger CD at litho and shrink by post-litho processing.[4] Here we carefully characterize two shrinking techniques and its efficacy on LCDU improvement. Fig. 2 shows two alternative approaches, i.e. DSA and cross-SADP.[5] We will carefully explore these four approaches for LCDU improvement with thorough characterization and analysis. Subsequent pattern transfer and the retention of the LCDU improvement and cost/quality trade-off will also be discussed. Defectivity learning will also be discussed.

With aggressive scaling of single-expose EUV lithography to the sub-7 nm node, stochastic variations play a prominent role in defining the lithographic process window. Fluctuations in photon shot noise, absorption and subsequent chemical reactions can lead to stochastic failure, directly impacting electrical yield. Fundamental characterization of the mode and magnitude of these variations is required to define the threshold for failure. In this work, a complementary series of techniques is enlisted to probe the nature and modulation of stochastic variation in single exposure EUV patterning. Unbiased line edge roughness (LER), local critical dimension uniformity (LCDU) and defect inspection techniques are employed to monitor the frequency of stochastic variations leading to failures in line/space and via patterning. Using this methodology, we explore the modulation of stochastic variations by different photoresists and illuminations, with emphasis on material and process down-selection for improved yield at the sub-7 nm node.

EUV resist characterizations for line and space patterning as a function of dose and illumination conditions for varying pitches down to 28 nm are discussed. The unintentional resist line top loss (LTL) after development has been monitored and analyzed for all experimental conditions. Furthermore, line top roughness (LTR) is introduced, which is a 3 stochastic metric characterizing in-plane roughness related to the top of the resist lines. The main characterization technique employed for this study is atomic force microscopy (AFM) with novel probing algorithms as well as novel tips with diameters down to 5 nm and aspect ratios of 10:1. Additionally, results acquired by critical dimension scanning electron microscopy and optical critical dimension scatterometry are presented. It was found that the unintentional LTL is resist- and pitch-dependent and can be higher than 9 nm at 16 nm half-pitch but does not correlate with line break defect density results. However, LTR measurements of small area scans at dense line/space pitches may be used to draw conclusions about line break defect densities and hence yield. The resist specific metrics, LTR and LTL, allow for fast and early-on evaluation of new chemical formulations and help to forecast pitch- and dose-dependent performance. Furthermore, the results can be used to improve resist model accuracy for optical proximity correction calculations.

With the insertion of EUV lithography into high volume manufacturing, mature lithographic materials and processes are required on multiple fronts. Not only do lithographic materials require optimization to reduce stochastic effects; processing techniques, underlying films, and auxiliary processes such as rinse are also known to have important impacts on the ability to yield sub-36nm pitch devices. In this paper we will describe the contribution that resist maturity, improved underlayers, rinse materials, and process parameters such as develop optimization and improved hardware have on yield improvement.

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the second generation of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. A typical defect Pareto for EUV line-space patterning is dominated by bridging defects and pattern collapse. Regarding pattern collapse, careful attention needs to be paid to optimizing the rinse process to avoid the large forces that cause collapse during drying. In this paper, we present an optimized rinse technology that works to prevent that pattern collapse, especially on EUV line/space patterns below 40nm pitch. Additionally, this paper reviews the ongoing progress in track-based processes (coating, developer) that are required to enable EUV patterning. This work is especially focused on defect mitigation during film coating and resist developing processes, which have a direct effect on the occurrence of bridging defects during pattern transfer.

Background: With aggressive scaling of single-expose (SE) extreme ultraviolet (EUV) lithography to the sub-7-nm node, stochastic variations play a prominent role in defining the lithographic process window (PW). Fluctuations in photon shot noise, absorption, and subsequent chemical reactions can lead to stochastic failure, directly impacting electrical yield. Aim: Fundamental characterization of the mode and magnitude of these variations is required to define the threshold for failure. Approach: A complementary series of techniques is enlisted to probe the nature and modulation of stochastic variation in SE EUV patterning. Unbiased line edge roughness (LER), local critical dimension uniformity (LCDU), and defect inspection techniques are employed to monitor the frequency of stochastic variations leading to failures in line/space (L/S) and via patterning. Results: When characterizing different resists and illumination conditions, there is no change in unbiased LER or via LCDU with increasing critical dimension (CD). Stochastic defect density is correlated with CD for both L/S and via arrays, and there is a strong correlation with L/S electrical yield data. Conclusions: Traditional 3σ LER and via LCDU measurements are not sensitive enough to define and improve PW. For PW centering and yield improvement, stochastic defect inspection is a necessity.

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the second generation of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. In addition, CD uniformity improvements must be continued to meet patterning performance requirements. Tokyo Electron Limited (TELTM) and IBM Corporation are continuously developing manufacturing quality processes for EUV.

The key challenge for enablement of a 2nd node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma (291x) and e-beam systems, find it difficult to detect the main yield-detracting defects post-develop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield. This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors .

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the full scaling entitlement of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. In addition, CD uniformity and LWR/LER must be improved in terms of patterning performance. Tokyo Electron Limited (TEL™) and IBM Corporation are continuously developing manufacturing quality processes for EUV. In this paper, we review the ongoing progress in coater/developer based processes (coating, developing, baking) that are required to enable EUV patterning.

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates for enabling the next generation devices, for 7nm node and beyond. As the technology matures, further improvement is required in the area of blanket film defectivity, pattern defectivity, CD uniformity, and LWR/LER. As EUV pitch scaling approaches sub 20 nm, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse and eliminate film related defect. IBM Corporation and Tokyo Electron Limited (TELTM) are continuously collaborating to develop manufacturing quality processes for EUVL. In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.

Successful pattern transfer from the photoresist into the substrate depends on robust layers of lithographic films. Typically, an alternating sequence of inorganic (most often Si containing) and organic hardmask (HM) materials is used. Pattern transfer occurs then by using reactive ion etch (RIE) chemistry that is selective to one particular layer (such as: flurorinated RIE for Si HM). The impact of these RIE gases onto the layers acting as hardmask for the layer to be etched is typically neglected, except for known sputtering effects. We found that components of the RIE gases can penetrate deep into the “inert” layers and significantly modify them. For example, nitrogen used as component to etch spin-on carbon layers was found to travel up to 70 nm deep into Si HM materials and create layers with different material properties within this film. The question is being raised and discussed to which extent this atom implantation may impact the pattern transfer of the ever shrinking features.

Initial readiness of EUV (extreme ultraviolet) patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. With the substantial cost of EUV exposure there is significant interest in extending the capability to do single exposure patterning with EUV. To enable this, emphasis must be placed on the aspect ratios, adhesion, defectivity reduction, etch selectivity, and imaging control of the whole patterning process. Innovations in resist materials and processes must be included to realize the full entitlement of EUV lithography at 0.33NA. In addition, enhancements in the patterning process to enable good defectivity, lithographic process window, and post etch pattern fidelity are also required. Through this work, the fundamental material challenges in driving down the effective k1 factor will be highlighted.

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

The key challenge for enablement of a second node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma and e-beam systems, find it difficult to detect the main yield-detracting defects postdevelop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield. This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors.

The Photopolymer Science and Technology Award No. 092100, the Best Paper Award 2009, was presented to Dario L. Goldfarba, Libor Vyklickya, Sean D. Burnsa, Karen Petrillob, John Arnoldb, Anthony Lisib, Dirk Pfeiffera, Daniel P. Sandersc, Robert D. Allenc, David R. Medeirosb, Dah Chung Owe-Yangd, Kazumi Nodae, Seiichiro Tachibanae, and Shozo Shiraie (aIBM T.J. Watson Research Center, bIBM Systems & Technology Group, cIBM Almaden Research Center, dShin-Etsu MicroSi, Inc., eShin-Etsu Chemical Co.) for their outstanding contribution published in the Journal of Photopolymer Science and Technology, 21(3), 397-404 (2008), entitled "Graded Spin-on Organic Bottom Antireflective Coating for High NA Immersion Lithography".

A spin-on organic Graded Bottom AntiReflective Coating (GBARC) was developed to enable appropriate reflectivity control during advanced photoresist patterning using 193nm immersion lithography up to 1.35 NA (limits of hyper-NA lithography using water as immersion fluid). This novel technology constitutes a simplified reflectivity control approach over more conventional schemes such as dual-layer BARCs, trilayer stacks or single layer BARCs. The GBARC layer is formed upon vertical phase separation of optically tuned polymeric components present in a GBARC casting solution during the spin-coating and post-applied baking steps. The substrate surface energy is found to dictate the direction of the spatial assembly for any given phase-separating polymer blend combination. The index of refraction (n193) of the GBARC polymeric components is approximately matched to that of the photoresist and substrate layers for optimum reflectivity control, while the extinction coefficient (k193) increases gradually towards the substrate. Analytical characterization of the varying optical constants throughout the GBARC film is achieved by Variable Angle Spectroscopic Ellipsometry (VASE) which allows for a quantitative description of the optical gradient present within the GBARC layer. The optical gradient sharpness is shown to be impervious to total GBARC thickness variations at constant relative polymer mass loading as well as changes in the relative mass loading of polymeric components at fixed total GBARC thickness. Also, the link between image profile afforded by various levels of reflectivity control and the mechanical stability of photoresist nanostructures is investigated at 1.2NA by designing GBARC formulations with variable residual reflectivity. Substrate reflectivity in excess of 1% is shown to limit the focus-exposure window due to pattern collapse. Last, adhesion of 193 nm photoresist patterns to a GBARC film is compared to a commercially available single layer BARC. Enhanced adhesion is demonstrated in the case of the GBARC surface, despite the low surface energy that typifies GBARC layers

We have investigated a number of key resist factors using EUV lithography including activation energy of deprotection, and acid diffusion length. Our standard high activation resist material, MET-2D (XP5271F), is capable of robust performance at CDs in 40 nm regime and thicknesses above 100 nm. Below 100 nm film thickness, controlling acid diffusion becomes a difficult challenge. We have also developed a low activation resist (XP6305G) which shows superior process window and exposure latitude at CDs in the 35 nm regime. This resist is optimal for 80 nm film thickness. Lastly, we have demonstrated 25 nm 1:1 resolution capability using a novel chemical amplification resist called XP6627. This is the first EUV resist capable of 25 nm resolution. The LER is also very low, 2.7 nm 3σ, for the 25 nm features. Our first version, XP6627G, has a photospeed of 40 mJ/cm2. Our second version, XP6627Q, has a photospeed of 27 mJ/cm2. Our current focus is on improving the photospeed to less than 20 mJ/cm2. The outstanding resolution and LER of this new resist system raises the possibility of extending chemically amplified resist to the 22 nm node.

The growing complexity of photolithography processes necessitates stringent defect monitoring to meet the increasingly rigorous yield requirements. Mitigation of defectivity at the track level involves both product wafer scans, as well as blanket wafer inspections for process monitoring and tool qualification. Some of the common defect types that are characteristic of the track process are comets, striations, water marks, chuck marks, edge effect etc [1]. In this work, we review two case studies that highlight the benefit of using laser-based scattering imaging for detecting coating-induced defects in blanket wafers [2]. First, we used a whole wafer, laser-based scattering image to detect, as well as quantify, a buildup of material near the wafer center. Grid analysis of the whole wafer image enabled us to bin out the defective regions of the wafer surface, and as a result automatically flag defective monitor wafers. Achievement of process improvement is reflected in the post-change process scan images. This methodology of process signature monitoring led to the optimization of the spin coating process which was implemented by the track team. In the second case, whole wafer laser scattering imaging was again successfully used to visually capture the spin coating classical striation signature in a film from a trilayer stack. This was further quantified by using a spectroscopic ellipsometer, which clearly highlighted the thickness variation of the resist film as a function of radius across the wafer with maximum thickness variation was observed near the center of the wafer surface. Further studies for this layer will focus on a quantification strategy for verification of process anomaly. This work was performed by IBM Research and Development at various facilities.

With current progress in exposure source power, novel resist materials, and post processing techniques, EUV is getting closer to the production environment. As reported continuously, SEMATECH established cycles of learning program. The data generated from the program has been utilized to measure current state of the art of EUV photoresist for production or pilot line use. Thanks to SEMATECH core and associate members’ attention to the project, numerous EUV samples have been tested and they were based on the best performing EUV resists from associate members. This year we completed the evaluations for under-layers, lines and spaces, and contact holes. We also applied track based techniques to drive both low line edge roughness control and enlarge the process window with techniques such as FIRM TM and track based smoothing process. In this paper we will discuss about the results from cycles of learning test and show post-processing results of the three best line and space resists when combined with different FIRM TM materials.

Evaluation of resist shrinkage and precision by critical dimension scanning electron microscope (CD-SEM) for EUV resist patterns at around 20 nm exposed by 0.33 NA EUV tool was conducted. To investigate interaction between EUV resist and electron beam, an accurate and fast measurement method of resist shrinkage was established. Our method can avoid saturation of shrinkage at large dose conditions which was a demerit in conventional method. By applying the new method, pattern size dependence of shrinkage was measured with various line and space (L/S) patterns down to 20 nm. The result shows that resist shrinkage of fine L/S EUV resist pattern largely depends on line width rather than space width. A well-known trade-off relationship between shrinkage and precision was observed for EUV resist pattern as well as ArF resist pattern. Shrinkage of 1.6 nm and precision of 0.13 nm for 18 nm EUV resist pattern were obtained at a typical CD-SEM condition. We also measured shrinkage and precision for a dense L/S pattern at various exposure focus and dose conditions using a FEM wafer to examine the impact of process variability. To investigate the influence of EUV shadowing effect, we measured them for both horizontal and vertical patterns at different slit locations in exposure field. No systematic change of shrinkage and precision was observed through exposure focus and dose in the process window across slit location for both horizontal and vertical L/S patterns.

The use of organic solvents in the development of chemically amplified (CA) resists has been known since the introduction of DUV lithography into manufacturing over twenty years ago [1,2]. In this approach a negative tone image is produced using an aqueous base developable positive tone resist developed in an organic solvent. Recently there has been an increased interest in negative tone imaging due to superior performance for specific masking levels such as narrow trenches and contact holes [3]. Negative tone imaging of this type is based on differences in the polarity between the exposed and unexposed regions of the resist film. The dissolution contrast can be optimized by selecting a solvent with the proper match of solubility parameters (polarity, hydrogen bonding and dispersion) to attain good solubility of the relatively nonpolar unexposed resist and poor solubility of the deprotected acidic exposed film. Another approach is to tune the properties of the resist polymer for a given solvent, creating a new optimized resist. We have explored a third methodology to achieve a high contrast solvent developable system without a need to modify resist or solvent. In this report we describe a process that exploits the differences in solubility between ionic and organic materials. In this method an ionic species is introduced into the resist film following post-exposure bake to alter the polarity in such way that the resist contrast can be improved in organic solvent development. We describe processes using pre-rinses and developers containing salts. Lithographic response, characterized using contrast curves and imaging, is presented for a variety of resist platforms. We show evidence for ionic incorporation into the resist film using SIMS, XPS, QCM and FTIR characterization. We demonstrate the practical applicability of this method to 248nm, 193nm, e-beam and EUV exposures.

Resists for advanced mask-making with high-voltage electron-beam writing tools have undergone dramatic changes over the last three decades. From PMMA and the other early chain-scission resists for micron dimensions to the aqueous-base-developable, dry-etchable chemically amplified systems being developed today, careful tuning of the chemistry and processing conditions of these resist systems has allowed the patterning of photomasks of increasing complexity containing increasingly finer features. Most recently, our research efforts have been focused on a low-activation-energy chemically amplified resist based on ketal-protected poly(hydroxystyrene). These ketal resist systems, or KRSs, have undergone a series of optimization and evaluation cycles in order to fine-tune their performance for advanced mask-fabrication applications using the 75-kV IBM EL4+ vector scan e-beam exposure system. The experiments have led to an optimized formulation, KRS-XE, that exhibits superior lithographic performance and has a high level of processing robustness. In addition, we describe advanced formulations of KRS-XE incorporating organometallic species, which have shown superior dry-etch resistance to novolak-based resists in the Cr etch process while maintaining excellent lithographic performance. Finally, current challenges facing the implementation of a chemically amplified resist in the photomask manufacturing process are outlined, along with current approaches being pursued to extend the capabilities of KRS technology.

Thin film imaging resists (TSI and Bilayer systems) confine the imaging to a thin resist film (in the case of a bilayer system) which is subsequently transferred to a thicker polymeric underlayer. This approach has a number of potential advantages including increased ability to print high aspect ratios at small feature sizes, better resolution at a given depth of focus (DQF), and minimization of resist substrate interactions including resist "footing, " standing wave formation and reflective notching caused by topography. Continued progress in single layer resist technology has been able to meet the current manufacturing requirements and the more complex TSI approaches have not yet been required. However, the requirements for imaging features below 0.18 microns, the desire to extend high NA 248nm exposure technology and anticipated shift to 193nm exposure tools has led to renewed interest in thin film imaging approaches. In this report we will describe new chemistry developed for bi layer resist systems for use at 248 nm in both positive and negative tone.

For projection printing imaging systems with fixed or restricted illumination modes, pupil filters may enhance imaging for select features by blocking rays of light that negatively contribute to imaging. A method to design pupil filters for the optimum printing of a select feature type and size is presented. With this method, a series of pupil filters have been developed and are being tested to enhance the resolution of the Albany Alpha Demo Tool (ADT, 0.25NA) in order to enable resist and process development at feature sizes relevant to the 10 and 7nm nodes. By only allowing light to propagate to the wafer that positively contributes to imaging, six filters have been custom designed to optimize printing of the following sub-resolution feature types and sizes: 22 and 19 nm HP lines, 24 and 21 nm HP contacts, and 27×22 nm HP rectangular contacts. Development and installation of enabling hardware on the scanner is complete, six filters have been manufactured and imaging in resist has validated the concept. Over 20% improvement in tool resolution has been achieved for 22nm HP lines, allowing resist process development for NXE3300 conditions on the ADT. This paper discusses the theory behind the filter designs, the experimental in-resist evaluations, and other aspects of the development, to include challenges caused by the filters with slit uniformity, stray light, and reticle alignment.

Roughness control is a key technical issue in extreme ultraviolet (EUV) lithography. It applies to both line and space (L/S) and contact hole (C/H) structures. Recently, SEMATECH and Tokyo Electron Limited (TEL) developed several track-based techniques, including developer optimization, FIRM™ (Finishing up by Improved Rinse Material), and smoothing to reduce structural roughness. The combination of these techniques improved line width roughness (LWR) about 25% from the 2011 baseline of 32 nm L/S. C/H structures were also tested with the combination process. This paper describes our latest L/S and C/H roughness performance post-lithography and postetch. A feasibility study of negative tone develop (NTD) resists for EUV is also included.

During exposure in an EUV scanner, photoresist and other materials coated on a wafer are known to outgas various species. As a requirement to pattern materials in an ASML NXE scanner, these materials need to be screened for outgassing and possible optics contamination. As part of the testing process, a resist-coated wafer is exposed in a vacuum chamber mimicking the conditions inside an EUV scanner. The resist exposure source can be either EUV photons or electron beam (e-beam). This presentation will cover the results to date on a SEMATECH program to study resist outgassing from both the commercial system from EUV Tech and a custom Resist Outgassing and Exposure (ROX) tool. The EUV Tech results reported will be based on electron exposures of the photoresist, and the ROX results reported will be based on EUV photon exposures of the photoresist. The results reported will cover both tools and the measurements of over 80 commercial photoresists.

This paper demonstrates a new simulation-based methodology for optimizing critical dimension (CD) bias for contact holes (CH) arrays using several different extreme ultraviolet (EUV) resists that were fully calibrated and verified with physical resist models. The bias for CH was optimized using local CD uniformity (CDU) 3-sigma as a cost function. The CD sigma variations of near-neighbor contact holes were simulated as a function of dose-to-size and mask bias, averaged over a large number of stochastic trials. There is a distinct bias for minimum CD sigma accompanied by an increase in the process window. The results are confirmed with wafer data. We will discuss the results in terms of EUV photon shot noise coupled with resist parameters. The simulation results will be used to predict a parameter space for EUV resist that can optimize line edge roughness (LER)/resolution/process window and CDU. Finally, various tradeoffs will be presented that will enable the process to perform in a high volume manufacturing environment.

Line Edge Roughness (LER) continues to be a serious problem for high resolution 193 nm (ArF), E-beam and EUV resists despite years of research. Changes to the resist formulations, the use of low molecular weight (MW) materials, such as molecular glass resists, and special developers have all been used in attempts to minimize LER. In addition, much recent work has focused on post development processes such as rinses, special coatings and thermal treatments to reduce roughness. However there remains a lack of understanding of the origins of LER. Recently researchers have described interesting results based on the use of in situ high speed AFM to characterize LER during development. 1 In this report we describe a complementary technique wherein the evolution of the roughness of the resist line is measured at different times during the development process. This is accomplished by using a specially designed flow cell 2-5 to control the developer contact time for a series of identically patterned fields and measuring the partially developed patterns with scanning electron microscopy (SEM). We will describe the results for different resist chemistries at 248 nm (KrF). In one aspect of this study, we examine resists that have been patterned at different aerial image contrast (AIC) to systematically probe its effect on LER 6 for a given resist. We intend to extend this work to different exposure systems including 193 nm, EUV and electron-beam.

Traditional patterning stacks for deep ultraviolet patterning have been based on a trilayer scheme with an organic planarizing layer, silicon antireflective coating or organic bottom antireflective coating, and photoresist. At an extreme ultraviolet (EUV) wavelength, there is no longer a need for reflectivity control. This offers an opportunity to look at different types of underlayers for patterning at sub-36 nm pitch length scales. An alternate hardmask can be used to develop a low aspect ratio patterning stack that can enable a larger process window at sub-36 nm pitch resolution. The hardmask layer under the resist has the potential for secondary electron generation at the resist/hardmask interface to improve resist sensitivity. This work explores EUV patterning on deposited hardmasks of various types such as silicon oxides and metal hardmasks. It also details the challenges of patterning directly on an alternate underlayer and approaches for improving patterning performance on such layers.

The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k 1 -value when printing with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography technology as seen from an end-user perspective is summarized and the current values of the most important metrics for each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into production at the 14 nm technology node.

Controlling line width roughness (LWR) is a critical issue in extreme ultraviolet lithography (EUVL). High sensitivity, high resolution, and low LWR are required for EUV lithography resist. However, simultaneously achieving optimal properties through chemical tuning alone is difficult. The track process is one of the factors that impacts LWR. Enhancing track processes in EUV lithography is thus critical to controlling LWR. This paper describes an approach to mitigating LWR based on optimizing track-based and etch-based processes. It also presents the results of our newly developed track-based smoothing process as well as the results of combining several track-based techniques. The latest LWR performance from using track-based techniques, optimized track processes, and etch-based techniques will be highlighted.

A new contamination resistant 248nm DUV resist (ESCAP-E) has been developed to alleviate the difficulties encountered with the environmental contamination sensitivity of chemically amplified DUV photoresists. The formulation and processing of ESCAP-I; have been designed to permit thermal annealing of resist films to reduce the free volume and diffusivity of airborne contaminants into the resist film. The resist formulation is robust enough to permit post exposure bake delays of up to four hours without change or reduction of resist lithographic performance. The lithographic performance evaluated on 0.50NA 248nm steppers indicates linearity to 0.25μm, excellent exposure latitude and depth of focus.

Fully functional 512Kb static-random access memory (SRAM) devices containing more than 3.6 million transistors have been successfully fabricated in a 0.25 μm complementary metal oxide semiconductor (CMOS) technology using compact storage ring X-ray lithography thus demonstrating the functionality of the X-ray lithography infrastructure. A lithographic performance comparison was made between x-ray lithography and optical (excimer laser) lithography by fabricating SRAM devices using both lithographic techniques. The excellent process latitude and dimension control available for x-ray lithography is reflected in this comparison. A comprehensive discussion of the advantages of x-ray lithography is discussed in this paper.

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for