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Integrating In-Ga-Zn-oxide (IGZO) channel transistors in silicon-based ecosystems requires the resilience of the channel material to hydrogen treatment. Standard IGZO, containing 40% In (metal ratio) suffers from degradation under forming gas anneal (FGA) and hydrogen (H) driven positive bias temperature instability (PBTI). We demonstrate scaled top-gated ALD transistors with an In-poor (In $\le$ 17%) IGZO channel that show superior resilience to hydrogen compared to the In-rich (In=40%) counterpart. The devices, fabricated with a 300-mm FAB process with dimensions down to $W_\mathrm{CH} \times L_\mathrm{TG} = 80 \times 40 \mathrm{nm}^2$, show excellent stability in 2-hour 420$^\circ$C forming gas anneal ($0.06 \le \left| \Delta V_{\mathrm{TH}} \right| \le 0.33\mathrm{V}$) and improved resilience to H in PBTI at 125$^\circ$C (down to no detectable H-induced $V_{\mathrm{TH}}$ shift) compared to In-rich devices. We demonstrate that the device degradation by H in the FGA is different from the H-induced VTH instability in PBTI, namely oxygen scavenging by H and H release from a gate-dielectric into the channel, respectively, and that resilience to H in one process does not automatically translate to resilience to H in the other one. This significant improvement in IGZO resilience to H enables the use of FGA treatments during fabrication needed for silicon technology compatibility, as well as further scaling and 3D integration, bringing IGZO-based technologies closer to mass production.

This paper addresses the question: Can spintronic circuits based on Magnetic Tunnel Junction (MTJ) transducers outperform their state-of-the-art CMOS counterparts? To this end, we use the EPFL combinational benchmark sets, synthesize them in 7 nm CMOS and in MTJ-based spintronic technologies, and compare the two implementation methods in terms of Energy-Delay-Product (EDP). To fully utilize the technologies potential, CMOS and spintronic implementations are built upon standard Boolean and Majority Gates, respectively. For the spintronic circuits, we assumed that domain conversion (electric/magnetic to magnetic/electric) is performed by means of MTJs and the computation is accomplished by domain wall based majority gates, and considered two EDP estimation scenarios: (i) Uniform Benchmarking, which ignores the circuit's internal structure and only includes domain transducers power and delay contributions into the calculations, and (ii) Majority-Inverter-Graph Benchmarking, which also embeds the circuit structure, the associated critical path delay and energy consumption by DW propagation. Our results indicate that for the uniform case, the spintronic route is better suited for the implementation of complex circuits with few inputs and outputs. On the other hand, when the circuit structure is also considered via majority and inverter synthesis, our analysis clearly indicates that in order to match and eventually outperform CMOS performance, MTJ efficiency has to be improved by 3-4 orders of magnitude. While it is clear that for the time being the MTJ-based-spintronic way cannot compete with CMOS, further transducer developments may tip the balance, which, when combined with information non-volatility, may make spintronic implementation for certain applications that require a large number of calculations and have a rather limited amount of interaction with the environment., Comment: This work was supported by imec Industrial Affiliation Program on Exploratory Logic Devices. It has also received funding from the European Union Horizon Europe research and innovation programme within the project SPIDER under grant agreement No 101070417