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Abstract The Deep Underground Neutrino Experiment (DUNE) is a leading experiment in neutrino physics which is presently under construction. DUNE aims to measure the yet unknown parameters in the three flavor oscillation case which includes discovery of leptonic CP violation, determination of the neutrino mass hierarchy and measuring the octant of θ 23. Additionally, the ancillary goals of DUNE include probing the subdominant effects induced by possible physics beyond the Standard Model (BSM). One such new physics scenario is the possible presence of Large Extra Dimension (LED) which can naturally give rise to tiny neutrino masses. LED impacts neutrino oscillation through two new parameters, — namely the lightest Dirac mass m 0 and the radius of the extra dimension R ED (< 2 μm). At the DUNE baseline of 1300 km, the probability seems to be modified more at the higher energy (≳ 4 − 5 GeV) in presence of LED. In this work, we attempt to constrain the parameter space of m 0 and R ED by performing a statistical analysis of neutrino data simulated at DUNE far detector (FD). We illustrate how a combination of the standard low energy (LE) neutrino beam and a medium energy (ME) neutrino beam can take advantage of the relatively large impact of LED at higher energy and improve the constraints. In the analysis we also show the role of the individual oscillation channels (ν μ → ν e , ν μ → ν μ , ν μ → ν τ ), as well as the two neutrino mass hierarchies.

Abstract Complex spatial light modulator (SLM), which can simultaneously control the amplitude and phase of light waves, is a key technology for wide-range of wave-optic technologies including holographic three-dimensional displays. This paper presents a flat panel complex spatial light modulator that consists of dual in-plane switching liquid crystal panels with double-degrees of freedom of voltage inputs. The proposed architecture features single-pixel level complex light modulation enabling complex light modulation in entire free space, which is most contrast to conventional macro-pixel based complex modulation techniques. Its complex light modulation capability is verified with theoretical simulation and experimental characterization, and a three-dimensional holographic image reconstruction without conjugate noise. It is believed that the proposed flat panel complex SLM can be an essential device for a wide range of advanced wave optic technologies.

Obtaining true random numbers is of great importance for cryptography, however, it can be challenging to obtain a large bit rate. Here, the authors make use of the oscillating behaviour of a Mott memristor, which exhibit rapid oscillations, and therefore a large bit rate, alongside impressive endurance.

Abstract A memristive stateful neural network allowing complete Boolean in‐memory computing attracts high interest in future electronics. Various Boolean logic gates and functions demonstrated so far confirm their practical potential as an emerging computing device. However, spatio‐temporal efficiency of the stateful logic is still too limited to replace conventional computing technologies. This study proposes a ternary‐state memristor device (simply a ternary memristor) for application to ternary stateful logic. The ternary‐state implementable memristor device is developed with bilayered tantalum oxide by precisely controlling the oxygen content in each oxide layer. The device can operate 157 ternary logic gates in one operational clock, which allows an experimental demonstration of a functionally complete three‐valued Łukasiewicz logic system. An optimized logic cascading strategy with possible ternary gates is ≈20% more efficient than conventional binary stateful logic, suggesting it can be beneficial for higher performance in‐memory computing.

Memristive neural networks perform vector matrix multiplication efficiently, which is used for the accelerator of neuromorphic computing. To train the memristor cells in a memristive neural network, the analog conductance state of the memristor should be programmed in parallel; otherwise, the resulting long training time can limit the size of the neural network. Herein, a novel parallel programming method using the self‐limited analog switching behavior of the memristor is proposed. A Pt/Ti:NbOx/NbOx/TiN charge trap memristor device for the programming demonstration is utilized, and a convolutional neural network is emulated to train the MNIST dataset, based on the device characteristics. In the simulation, the proposed programming method is able to reduce programming time to as low as 1/130, compared with the sequential programming method. The simulation suggests that the programming time required by the proposed method is not affected by array size, which makes it very promising in a high‐density neural network.

Memristive stateful logic enables energy‐ and cost‐efficient in‐memory computing, which is desirable for edge computing in the coming Internet of Things (IoT) era. Researchers have recently developed various stateful logic gates and have shown viable computing applications based on ideal memristive characteristics. However, few studies have demonstrated a system‐level in‐memory computing operation that can address the practical issues affecting device realization. Herein, a practically viable stateful logic device based on a 1‐transistor−1‐memristor (1T1M) array structure is proposed, considering the inherently stochastic memristor characteristics. Details on how to select the viable stateful logic gates in a given memristor are shown, and as an example of logic cascading, they are implemented in a device to operate a multibit carry look‐ahead adder. Then, an in‐memory computing layout that can perform all of the computing functions—data storing, transferring, and executing—inside the memory, addressing data traffic issues, is suggested. Finally, a software/hardware mixed stateful logic emulator that can virtually mimic array‐level in‐memory computing hardware based on cell‐level memristive characteristics is demonstrated.