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In this study, a novel circuit model was proposed for the design of multifunction integrated diplexers with frequency division, frequency selection, and power division functions. The proposed highly integrated multifunctional diplexer mainly comprises only two different-frequency multimode resonators and two isolation resistors, which results in a compact circuit size. The distributed coupling technique was adopted to integrate the two multimode resonators. One resonator was used to form a channel passband, and the other resonator was used to form another channel passband. Moreover, each channel passband can be independently designed and flexibly allocated. The two resistors loaded between the output feeding lines were introduced to improve the impedance matching of the output ports and the isolation between the output ports for each channel. The coupling structures, theoretical analysis, and design procedure for the proposed multifunction integrated diplexers are described. For demonstration, multifunction integrated diplexers with second-order and third-order filtering responses were designed and fabricated using microstrip technology. The experiment and simulation results were consistent and indicated satisfactory in-band and out-of-band performance.

This study focused on the design principle and implementation of a high-frequency, wide-range frequency synthesizer by using a dual control path phase-lock loop (PLL) and a varactorless oscillator controlled by inductive–capacitive (LC-type) voltage (i.e., a voltage-controlled oscillator, VCO). Without a varactor in the LC tank, the tuned-transducer oscillator with Q-enhanced functionality can easily arrive at the requirements of high-frequency wide-range low-noise operations. We utilized a difference tuned varactorless VCO to create two different KVCOs and applied it to a dual control path PLL architecture to obtain wide tuning range and more favorable phase noise. In addition, a high-speed current-mode logic divider was employed given its high speed (because of the use of a transformer inductor), extremely high operation frequency, and wide-range. The proposed PLL was assembled using the standard 0.13-μm CMOS technology on a 0.95 × 1.05 mm2 chip. The PLL dissipated 40 mW at a 1.2 V supply. The measurement of phase noise at 17.64 GHz was − 98.12 dBc/Hz at a 1 MHz offset.

Pr-doped ZnO thin films (Zn1−xPrxO) (x = 0.00, 0.01, 0.02, 0.04) were prepared on fluorine-doped tin oxide substrates by means of the sol–gel method and spin coating technology, followed by rapid thermal annealing treatment at 800 °C. The influence of Pr content on the structural and optical properties of the Zn1−xPrxO thin film was examined and discussed. The wurtzite hexagonal structural characteristics were investigated by X-ray diffraction analysis, and Pr3+ substitution for Zn2+ ions was indicated. Finally, the typical bipolar current-voltage switching curves and electrical conduction model of Zn1−xPrxO film resistive random access memory devices were discussed and investigated for low resistance state/high resistance state in the initial forming process.

In this paper, the proposed voltage mode buck converter senses. The output voltage is compared with the reference voltage, and the error voltage is amplified by the error amplifier. Finally, through the PWM signal to achieve the circuit regulator effect. Compared with the current mode buck converter, the voltage-mode buck converter has better noise margin, low impedance power output and single feedback loop, making design and circuit analysis easier. The addition of the LDO circuit allows the buck converter to reach a stable voltage faster and turn off the LDO after the buck converter is stable to reduce unnecessary power waste.

In the next few years, the home energy management system trend of the smart home will become increasingly evident. From the application and development of recent years, the Bluetooth and Zigbee are the most valued by the industry. Of these two kinds of technology, Zigbee supports low cost and more number of nodes, and with its low power consumption, it is bound to become a major communication feature for the smart home technology. Because Zigbee SEP2.0 specification support multiple network technology features, a product can become compatible with a variety of communication methods to connect with the home network and achieve home automation of functional requirements, facilitating maximum performance of wireless applications.

A monolithic CMOS DC-DC converter with integrated power switches and a novel variable-frequency boundary conduction mode for feedback control is presented in this paper. Implemented in a 0.18-um CMOS technology, the operating frequency is from 90 kHz to 500 kHz and the power efficiency can achieve 92.6%. The total area including I/O pads is 1.1mm × 1.15mm.

This paper presents a variable current-controlled single-inductor dual-output DC-DC buck converter depending on difference loading currents in standard 0.18-μm CMOS n-well process. We intend for compensate system and according each loading current to make suitable dual cycle. Two outputs are specified at 1.8V and 1.2V operated at 800 KHz, the power conversion efficiency reaches 82%. The chip occupies 1.73 × 1.1 mm2.

Consider the structure of a self-oscillation power amplifier as a power line driver. Self-oscillation power amplifier was improved by the Class-D power amplifier. The traditional Class-D switching power amplifier is vulnerable to distortion limitation. Due to the non-linear continuous time nature of the self-oscillation, it possesses peculiar properties that enable the construction of a highly linear, high-efficiency line driver. In the thesis which has efficiency up to 53%, SFDR and THD are 53.6 dB and 52.8 dB respectively. A prototype has been fabricated in a 0.35-um CMOS process to the proposed circuit.

A direct digital frequency synthesizer (DDFS) using an analog-sine-mapping technique is presented in a 0.35-μm SiGe BiCMOS process. We intend to apply the translinear principle to develop a triangle-to-sine converter (TSC) that can achieve outputs with low harmonic content. The TSC is introduced for the DDFS to translate phase data to sine wave. Using this analog-interpolating technique, the DDFS, with 9 bits of phase resolution and 8 bits of amplitude resolution, can achieve operation at 5-GHz clock frequency and can further reduce power consumption and die area. The spurious-free dynamic range (SFDR) of the DDFS is better than 48 dBc at low synthesized frequencies, decreasing to 45.7 dBc worst case at the Nyquist synthesized frequency for output frequency band (0-2.5 GHz). The DDFS consumes 460 mW at a 3.3-V supply and achieves a high power efficiency figure of merit (FOM) of 10.87 GHz/W. The chip occupies 1.5 × 1.4 mm2.

To lower the supply voltage for high-frequency operation, a fully integrated frequency synthesizer, together with regenerative frequency-doubling and fractional phase-rotating techniques, is presented. The frequency-doubling circuit regenerates the tail signals at twice the frequency of the quadrature voltage-controlled oscillator (QVCO) to achieve larger output swing and higher operating frequency for the synthesizer. Additionally, a hybrid circuit utilizing a new folded regime for the first-stage divider and the phase-rotating circuit is developed in the prescaler. Under full-speed operation, the QVCO with the frequency doubler and the divider can work from a 0.5-V supply, whereas the synthesizer dissipates 12 mW. At 9.1-GHz carrier frequency, the measured phase noise is -104.5 dBc/Hz from 1-MHz offset.

Implemented in a standard 0.18-μm CMOS process, a 0.8/0.9-V 5.4-GHz low-power phase-locked loop (PLL) is presented. In the prescaler, the first-stage divide-by-2 prescaler is structed with LC-type VCO by inductance coupled to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing the threshold voltage to lower the operating voltage. As the building blocks are optimized for low-voltage and low-power operations, the fabricated 5.4-GHz PLL consumes a dc power of 4.8 mW from a 0.8/0.9-V and phase noise of −109.6 dBc/Hz at 1-MHz offset.

Without an extra on-chip accumulation-mode MOS varactor, a voltage-controlled oscillator (VCO) using a negative-transconductance back-gate tuned technique is demonstrated in a standard 0.18 μm CMOS process to achieve low-voltage, wide-range and high-frequency designs. Employing the varied p-n junction capacitance and the varied transconductance in the intrinsic-tuned regime, the VCO provides the tuning range of 9.95 to 11.05 GHz at a 0.6 V supply and dissipates below 4.35 mW. At 11 GHz carrier frequency, the measured phase noise is -110.4 dBc/Hz at a 1 MHz offset.

This study used 90-nm CMOS technology to design a power amplifier (PA) applicable to the V-band operation. The on-chip transformers play the power combination roles that were used to design the input, interstage and output impedance matching networks. To alleviate the power loss, the ground shielding technique is employed in proposed transformer. The measurement results indicated that the output power and OP 1dB achieve 13.2dBm and 11.6dBm, respectively. The gain was 10dB, the bandwidth is 20GHz, ranging from 55GHz to 75GHz, the power added efficiency was 4.1% at 60GHz, and the power dissipation was 430mW.

This paper proposes the class of the translinear (TL) circuits implementing a wide range of static nonlinear relationships in the current signal domain to computational such as generating products, quotients, vector magnitude and rational functions, which are implemented in a standard 0.35-µm SiGe technology. A shunt-feedback buffer principle is used in order to regulate its emitter voltage of translinear to generate sinusoidal wave. The resolution can be fine tune by adjusting the output current source. The circuits use no any capacitances and filters. The circuits are based on exploit the exponential current-voltage characteristic of bipolar transistors. The analysis of input, and output resistance and current-gain are depicted. The SFDR of sin wave resolution measurement is 55.23 dB at a 1-MHz and the power consumption is 102mW with the die areas 0.66×0.62 µm2.

Constructed from a current reused architecture for low power consumption, a cascode topology of an LC VCO and a divide-by-4 prescaler is used in a PLL. In the prescaler, the first-stage divide-by-2 divider is an injection locking circuit used to frequency lock to an incident signal to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing the threshold voltage to lower the operating voltage. Implemented with 1.8-V 0.18-μm CMOS, the PLL provides the phase noise of -121.67 dBc/Hz at 1-MHz offset and consumes 3.4 mW at 2.4 GHz.

The paper addresses the design and realization of a high-frequency and wide range frequency synthesizer based on a PLL together with a varactorless LC-type VCO and a push-push frequency doubler. In addition, a high-speed programmable divider using multi-phase selection is employed for channel switching. The proposed circuits were fabricated in a standard 90-nm CMOS process with a chip area of 0.8×1.1 mm2. The PLL dissipates 60 mW at a 1.2-V supply. The measured phase noise of the doubler at 35.28-GHz frequency is -90.42 dBc/Hz at a 1-MHz offset.

A new compact microstrip dual-band bandpass filter (BPF) based on multi-mode λ/4 stepped-impedance resonators (SIRs) with separate coupling paths is investigated. The dual-band BPF with a second-order bandpass response is composed of only two λ/4 SIRs, resulting in a small circuit size. A coupling gap and a common short-ended stub between the two coupled SIRs are used to create the electric and magnetic couplings with separate coupling paths. The bandwidths of the dual-band BPF can be well controlled by adjusting the coupling strengths of the two coupling paths. Thus, a greater design flexibility for the dual-band BPF can be obtained. For demonstration, a second-order dual-band BPF with a compact size of 0.14 λ g × 0.16 λ g has been designed and fabricated. A good agreement is achieved between simulation and measurement.

Fabricated in a 0.18-µm CMOS technology, a wide-range fractional-N frequency synthesizer with a phase-compensated technique is presented. While using a 630–960 MHz LC-type VCO, the synthesizer can provide the range of 55 to 960 MHz with a band-selecting structure to satisfy the ATSC applications. Using the phase-rotating concept, the synthesizer can achieve the fractional functionality, instead of the conventional ΔΣ interpolation. The measured results show phase noise is −123 dBc/Hz at 1-MHz offset. The lock time is below 6 µs from 640 MHz to 930 MHz.

A new programmable duty cycle corrector (PDCC) with variable duty cycle of output clock and synchronization of the input clock and output clock is proposed. Since the conventional pulse-width control circuits can adjust duty cycle but canpsilat synchronize the input and output clocks, the proposed PDCC uses a 2nd-order Delta-Sigma modulator to produce more several kinds of duty-cycle selection of clock signals with a 7-bit resolution. Simulated in a 0.18 um CMOS technology, the proposed PDCC can operate from 500 MHz to 800 MHz and the duty-cycle range of input clock can be operated from 10% to 90%. Moreover, the duty cycle of the output clock can be adjusted from 25% to 75% in a fine step of 0.78%.

In this paper, a fifth-order elliptic low-pass Gm-C filter using a linear transconductance is presented in a standard 0.18-mum CMOS technology. The tranconductor has a wide-range constant gain and uses fully differential source- degenerated operational transcconductance amplifier which introduces a folded-cascode output stage with common mode feedback circuit. The Gm is 1 mA/V with 0.5 Vp-p input range. The power consumption is 56 mW including the common- mode feedback circuit.

In this paper, a burst-mode clock and data recovery (CDR) circuit using a 1/4-rate clock technique is realized for optical communication system. The CDR circuit contains a phase detector and a muxed-oscillator to control the phase of the clocks. In-lock operation is accomplished on the first data transition, and after the first data the clocks are in phase for all data until the data transition is over. The CDR circuit is implemented with 0.18-/spl mu/m CMOS technology. The experimental results show that the proposed CDR circuit recover the incoming 1.8-Gb/s data.

A 0.35-/spl mu/m CMOS instrumentation amplifier with automatic gain control (AGC) system for the sensor interfaces is presented in this paper. The circuitry employs a chopper stabilization technique to significantly reduce the low-frequency noise and DC offset. The AGC is used in the system where the amplitude of an incoming signal can vary over a wide dynamic range. The AGC circuit provides relatively constant output amplitude in spite of the sensitivity of the sensor due to the parameter variations. Furthermore, the whole system has been kept fully differential operation in order to get higher immunity to environmental noise of supply voltages, clock feedthrough, charge injection, even harmonic distortion, etc. It features a gain of 53/spl plusmn/17 dB with 25-kHz bandwidth. The equivalent input noise is about 1.13 /spl mu/V/sub pp/ at 98.2-kHz chopper frequency.