Search

This article addresses the classical problem of determining the extrinsic resistances ( $R_{G}$ , $R_{S}$ , and $R_{D}$ ) of field-effect transistors (FETs) and, in particular, of high-electron-mobility transistors (HEMTs). The presented approach relies on small-signal measurements of open-channel transistors, as often proposed both for traditional metal–semiconductor FETs (MESFETs) and HEMTs. Unlike what is common practice with HEMTs, the method proposed here does not oversimplify the model of the active channel. On the contrary, we retrieve from the literature a possible analytical model for the open-channel HEMT and use it to determine the triplet of extrinsic resistances without the need of stressing the gate junction with too high currents. Another result of the approach, valid both for MESFETs and HEMTs, is a deterministic way to remove the contribution of the gate junction from the small-signal parameters of the measured devices. All extractions process data that are available on suitable ranges in frequency or in bias voltage, without taking to the limit the sweep parameters or seeking specific resonances. Also, optimizations are only allowed to refine the nominal values, not as the main technique of extraction. These goals are achieved by setting up different subproblems in the form of overdetermined linear systems and then solving by pseudoinversion. The validity of the approach is demonstrated on the measurements of devices from advanced HEMT technologies realized by OMMIC, both GaAs-based (40-nm gate length) and GaN-based (100 and 60 nm).

This paper is focused on the extraction of the noise parameters of a linear active device by exploiting both forward and reverse noise power measurements associated with different terminations. In order for load-pull measurements to yield a significant marginal improvement (as compared to forward measurements only) it is expected that the device under test should appreciably deviate from unidirectionality. For this reason, the source/load-pull technique is applied to frequencies at which the considered devices are still usable but their reverse noise factor exhibits a measurable dependence on the output terminations. Details on the test bench set up to the purpose, covering the 20–40 GHz frequency range, are provided. A characterization campaign on a 60 nm gate length, 4×35 µm GaN-on-Si HEMT fabricated by OMMIC is illustrated.

This paper presents the design and test results of a 6 to 18 GHz power amplifier MMIC fabricated with a Gallium Nitride process, using a reactively matched non-distributed architecture. This circuit exhibits a gain of 20 dB, input and output return losses of 10 dB, an average output power of 40.8 dBm with associated Power Added Efficiency (PAE) of 35 %. As compared with similar amplifiers previously reported, this two-stage circuit presents to our knowledge the best PAE across the full bandwidth with a size of only 13 mm2.

Motivated by the growing interest towards low-cost, restriction-free MMIC processes suitable for multi-function, possibly space-qualified applications, this contribution reports the extraction of reliable linear models for two advanced GaN-on-Si HEMT technologies, namely OMMIC&rsquo, s D01GH (100 nm gate length) and D006GH (60 nm gate length). This objective is pursued by means of both classical and more novel approaches. In particular, the latter include a nondestructive method for determining the extrinsic resistances and an optimizaion-based approach to extracting the remaining parasitic elements: these support standard DC and RF measurements in order to obtain a scalable, bias-dependent equivalent-circuit model capturing the small-signal behavior of the two processes. As to the noise model, this is extracted by applying the well known noise-temperature approach to noise figure measurements performed in two different frequency ranges: a lower band, where a standard Y-factor test bench is used, and an upper band, where a custom cold-source test bench is set up and described in great detail. At 5 V drain-source voltage, minimum noise figures as low as 1.5 dB and 1.1 dB at 40 GHz have been extracted for the considered 100 nm and 60 nm HEMTs, respectively: this testifies the maturity of both processes and the effectiveness of the gate length reduction. The characterization and modeling campaign, here presented for the first time, has been repeatedly validated by published designs, a couple of which are reviewed for the Reader&rsquo, s convenience.

This paper provides an assessment between two MMIC foundry processes for millimetre-wave high-performance receiver applications, namely, OMMIC’s 70 nm GaAs and 60 nm GaN-on-Si processes. To do so, a characterization and modelling campaign was carried out on transistors provided by OMMIC for the two processes, whose commercial names are D007IH (70 nm GaAs) and D006GH (60 nm GaN). The resulting models were employed to design several test vehicle Low-Noise Amplifiers (LNA) operating above 30 GHz. The GaAs LNAs have been manufactured and characterized, while the GaN-on-Si LNAs are being manufactured. The initial outcome of the assessment is that GaAs is still ahead if Noise Figure is the crucial and mandatory requirement. GaN-on-Si, on the other hand, proves to be a viable solution if a – slightly – higher Noise Figure is acceptable. Moreover, the benefits of GaN-on-Si, with respect to GaAs, are higher robustness, output power, linearity, and higher integration capability with CMOS technologies.

A unique direct parameter extraction method for the small-signal equivalent-circuit model of InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) is presented. $S$ -parameters measured at cut-off bias are used, at first, to extract the distribution factor $X_{0}$ for the base-collector capacitance at zero collector current and the collector-to-emitter overlap capacitance $C_{ceo}$ present in InP DHBT devices. Low-frequency $S$ -parameters measured at normal bias conditions then allows the extraction of the external access resistances $R_{bx}$ , $R_{e}$ , and $R_{cx}$ as well as the intrinsic HBT elements of the device. The terminal inductances of the device are extracted from high frequency $S$ -parameters by employing the intrinsic HBT elements extracted at low-frequency. Compared to other published direct parameter extraction techniques the proposed method is developed specifically for III-V based HBTs and avoids $S$ -parameters measured at the critical open-collector bias condition. The method is applied to an $1.5~\mu{\rm m}$ emitter width InP/GaAsSb/InP DHBT device and leads to excellent prediction of the measured $S$ -parameters in the 250 MHz – 65 GHz frequency range.

This paper presents the measured results of two circuits fabricated with a millimeter wave 100 nm Gallium Nitride on Silicon (GaN/Si) process. The first circuit is a 27-34 GHz power amplifier, presenting 6 W of output power in pulsed operation and 5.6 W in CW operation. The second circuit, using exactly the same process, is a 8-12 GHz Low Noise Amplifier presenting 1.3 dB noise figure from 11 to 13 GHz.