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The nanowire gate-all-around structure with the ultimate channel electrostatic integrity exhibits the best immunity to short channel effects and improved scaling capability compared with other multigate structures. In this article, both the tunneling current and capacitance models are developed simultaneously for nanowire tunneling field-effect transistors (FETs). Based on the same surface potential model, the developed current model and capacitance model share the common parameters and therefore can be easily integrated as a complete model for circuit-level simulations. Moreover, there is no iterative process involved during the model derivation indicating the models would be efficient for circuit simulations. The proposed models are also implemented into a circuit simulator with SPICE net-list to simulate the inverter, nand, and nor gates. Correct circuit behaviors obtained validate the model compatibility with the SPICE platform and usefulness for the further investigation of nanowire-based tunnel FET (TFET) circuits.

Overcoming the drawbacks of the existing ferroelectric tunnel junction (FTJ) models which ignore the dynamic or multi-domain switching behaviors, we develop a more comprehensive FTJ model by combining the Time-Dependent Landau-Ginzburg (TDLG) equations to solve the multi-domain dynamic switching of ferroelectric layer and the Non-Equilibrium Green Function (NEGF) to solve the tunneling current. The model successfully reproduces the experimental results of our fabricated metal-ferroelectrics-insulator-semiconductor (MFIS) FTJ. This model empowers us to predict both the dynamic and multi-state switching of FTJ, showing its promise for applications in the high-density data storage and analog computing.

We report the temperature-dependent operation of back-end-of-line (BEOL) compatible amorphous indium-gallium-zinc-oxide ( ${a}$ -IGZO) ferroelectric thin-film transistors (FeTFTs) with a large memory window (MW) more than 3 V. Our ${a}$ -IGZO FeTFTs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) stru- cture with Zr-doped HfO 2 (HZO) as the ferroelectric layer. Characteristics of ${a}$ -IGZO FeTFTs are investigated in the temperature range of −40 °C to 100 °C. We found that: Firstly, the remanent polarization ( ${P}_{\text {r}}$ ) of the HZO film increases with $2{P}_{\text {r}}$ from $\sim 35~ {\mu }\text{C}$ /cm 2 at −40 °C to $\sim 40~ {\mu }\text{C}$ /cm 2 at 100 °C. Secondly, enhancement in MWs at high temperatures is observed, achieving MWs larger than 3.5 V when the temperature is higher than 60 °C. Thirdly, for the threshold voltage ( ${V}_{\text {TH}}$ ) at high temperatures, there is a competition between the negative shift caused by higher carrier concentration in the ${a}$ -IGZO channel and positive shift due to the charge trapping at the floating gate in the MFMIS structure. This could be explored to realize good ${V}_{\text {TH}}$ stability.

We report high-performance amorphous Indium-Gallium-Zinc-Oxide nanowire field-effect transistors (α -IGZO NW-FETs) featuring an ultrascaled nanowire width ( $W_{NW}$ ) down to ~20 nm. The device with 100 nm channel length ( $L_{CH}$ ) and ~25 nm $W_{NW}$ achieves a decent subthreshold swing (SS) of 80 mV/dec as well as high peak extrinsic transconductance ( $G_{m,ext}$ ) of 612 μ S/μ m at a drain-source voltage ( $V_{DS}$ ) = 2 V (456 μ S/μ m at $V_{DS}$ = 1 V). The good electrical properties are enabled by using an ultrascaled 5 nm high-k HfO₂ as the gate dielectric, a water-free ozone-based atomic layer deposition (ALD) process, and a novel digital etch (DE) technique developed for indium-gallium-zinc-oxide (IGZO) material. By using low-power BCl₃-based plasma treatment and isopropyl alcohol (IPA) rinse in an alternating way, the DE process is able to realize a cycle-by-cycle etch with an etching rate of ~1.5 nm/cycle. The scaling effects on device performance have been analyzed as well. It shows that the downscaling of $W_{NW}$ improves the SS notably without sacrificing on-state performance, and the shrinking of $L_{CH}$ boosts the $G_{m,ext}$ . The ultrascaled α -IGZO NW-FETs could play an important role in applications where high performance and high density are highly desired.

In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ( $\alpha $ -IGZO n-FET) on a SiO2/Si (OI) substrate. The key digital figure-of-merits of the CMOS inverter are evaluated, including voltage gain, noise margin (NM), and power consumption. The highest process temperature of this work is 400 °C to enable back-end-of-line (BEOL) compatible logic functions in three-dimensional (3D) monolithic integration. Performance advantages in terms of smaller subthreshold swing ( SS ) and higher mobility are also achieved as compared with previously reported p- and n-FETs in CMOS inverters comprising a p-FET and an n-FET with process temperature below 400 °C. The Ge p-FET exhibits a high-field mobility, threshold voltage ( ${V}_{\text {TH}}$ ), and SS of 91 cm2/ $\text{V}\cdot \text{s}$ , −0.26 V, 225 mV/decade, respectively, and those for the $\alpha $ -IGZO n-FET are 58 cm2/ $\text{V}\cdot \text{s}$ , 0.34 V, 163 mV/decade, respectively. The CMOS inverter shows a voltage gain of 5.5 V/V, NMH of 0.33 V, NML of 0.22 V, and power consumption of less than 0.03 mW at ${V}_{\text {DD}}$ of 1 V.

A ferroelectric based electrostatic doping (Fe-ED) technique is proposed, as the alternative to chemical doping, providing non-volatile and programmable free electrons and holes for nanoscale devices. We show that Fe-ED achieves non-volatility and reconfigurability via the ferroelectric film inserted into the polarity gate, producing the reconfigurable nanosheet FETs (NSFETs) without the requirement of a constant bias. Thanks to the naturally formed lightly doped drain structures and the extremely high doping concentration over $1\times 10^{21}$ cm−3 in source/drain (S/D) regions, Fe-ED NSFETs exhibit the promising potential benefits for device scaling including the improved subthreshold swing, the suppressed drain-induced barrier lowering, and the ultralow S/D region resistance. Our study suggests a promising doping strategy of Fe-ED for versatile reconfigurable nanoscale transistors and highly integrated circuits.

The combination of the InAs/GaSb heterojunction and the line-tunneling mechanism is considered as one of the most promising approaches to simultaneously obtain high ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and low subthreshold swing (SS) in tunneling field effect transistors (TFETs). However, in an InAs/GaSb line-tunneling field effect transistor (LTFET), the isolation between the source and the drain is a big issue. The leakage current path could lead to complete loss of the OFF-state characteristics in extreme cases. The “cantilever” or “airbridge” structure is usually introduced to cutoff the leakage path. However, it also induces serious reliability problems and brings additional process complexity. In this article, an N+ doped buried drain is first proposed to form a reverse biased p-n junction with the $\text{P}\boldsymbol +$ source and effectively cuts the leakage current path off. The InAs $\boldsymbol /$ GaSb LTFETs with this buried drain technique exhibits ${I}_{ \mathrm{\scriptscriptstyle ON}} \boldsymbol / {I}_{ \mathrm{\scriptscriptstyle OFF}} > {10}^{{7}}$ and SS $\boldsymbol /$ dec for five decades of current. Besides the excellent performance, the buried drain technique keeps the device planar and brings no additional fabrication complexity, which is of great significance for future experimental investigation and the low power applications.

We experimentally investigated the dependence of ferroelectricity in Al-doped HfO2 (HAO) films on the annealing temperatures ranging from 600 °C to 800 °C. Increasing the annealing temperature from 600 °C to 700 °C yields an enhanced remnant polarization ( ${P}_{\text {r}}$ ), but a slight reduction in coercive field ( ${E}_{\text {C}}$ ). While the highest reported ${P}_{\text {r}}$ of $23.7~\mu \text{C}$ /cm2 for the HAO films can be obtained with an annealing temperature of 800 °C, an obvious degradation in the uniformity of both ${P}_{\text {r}}$ and ${E}_{\text {C}}$ is observed. In addition, as the annealing temperature increases, the HAO films suffer from the raised leakage current and the degraded endurance characteristics.

In this letter, we proposed and experimentally demonstrated a metal-insulator-semiconductor (MIS) ferroelectric capacitor with non-volatile programmable capacitance. By switching the polarization of the Al-doped HfO2 ferroelectric insulator with the external electric field, the depletion width of the semiconductor can be modulated, leading to the continuously adjustable capacitance of the device. Due to the non-volatility of ferroelectricity, the programmed capacitance is stable without the constant DC bias. We also proposed some potential applications of the capacitor in the data storage and circuit design.

Non-volatile multilevel optical memory is an urgent needed artificial component in neuromorphic computing. In this paper, based on ferroelectric based electrostatic doping (Fe-ED) and optical readout due to plasma dispersion effect, we propose an electrically programmable, multi-level non-volatile photonics memory cell, which can be fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. Hf0.5Zr0.5O2 (HZO) film is chosen as the ferroelectric ED layer and combines with polysilicon layers for an enhanced amplitude modulation between the carrier accumulation and the confined optical field. Insertion loss below 0.4 dB in erasing state and the maximum recording depth of 9.8 dB are obtained, meanwhile maintaining an extremely low dynamic energy consumption as 1.0–8.4 pJ/level. Those features make this memory a promising candidate for artificial optical synapse in neuromorphic photonics and parallel computing.

GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys. However, CVD is the dominant growth method in the industry, and it is therefore more easily transferred. This review is focused on the recent progress in GeSn CVD growth (including ion implantation, in situ doping technology, and ohmic contacts), GeSn detectors, GeSn lasers, and GeSn transistors. These review results will provide huge advancements for the research and development of high-performance electronic and optoelectronic devices.

In this work, we present an experimental demonstration of a content addressable memory (CAM) cell based on ferroelectric HfO2 field effect transistors (FeFETs). Our proposed ferroelectric CAM (FeCAM) utilizes a CMOS-compatible ferroelectric material, hafnium zirconium oxide (HZO), as the gate dielectric. We discuss operation of the FeCAM cell and propose a suitable architecture to realize in-memory computation as well as single clock cycle content-driven search. In addition, the HZO FeFET is analyzed for its intrinsic memory characteristic, and design considerations are identified for improving device and therefore projected system-level performance. Our results indicate that FeCAM is well-suited to accommodate demanding modern computational needs by sealing the gaps between conventional memory, logic, and continued device scaling.

For the first time, this study experimentally validates that the depolarization field ( ${E}_{\text {DE}}$ ) in the ferroelectric (FE) film leads to voltage gains in negative capacitance (NC) field-effect transistors (FETs). For both NCFETs with and without a floating gate, the steeper subthreshold swing (SS) and the enhanced ${I}_{\text {ON}}$ are achieved under dc and pulse measurements corresponding to the measured voltage gains ( dV int/ dV GS > 1). Furthermore, the voltage gains are theoretically calculated based on the depolarization theory and the voltage distribution across the gate-stack, showing good agreements with the measured results. In conclusion, ${E}_{\text {DE}}$ in an FE film produces the NC effect and the voltage gains. Even with ${P} /cm2, sufficient ${E}_{\text {DE}}$ is still produced in NCFETs to achieve improved electrical performance over the reference MOSFET. These findings suggest a way for low-voltage and high-reliability NCFETs.

The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corner spacer improves the inverter propagation delay of the baseline FinFET, the NC-FinFET requires the fin selective spacer with the spacer height up to the ferroelectric thickness for better capacitance matching. When the wire capacitance is ~3 times larger than the gate capacitance, the inverter propagation delay of the NC-FinFET with the fin selective spacer can be improved by ~8% against the full spacer design. However, with the consideration of process complexity, the air spacer may still be attractive in the NC-FinFET, since it does not suffer from the amplified gate capacitance.

Here we report the ZrOx-based negative capacitance (NC) FETs with 45.06 mV/decade subthreshold swing (SS) under ± 1 V VGS range, which can achieve new opportunities in future voltage-scalable NCFET applications. The ferroelectric-like behavior of the Ge/ZrOx/TaN capacitors is proposed to be originated from the oxygen vacancy dipoles. The NC effect of the amorphous HfO2 and ZrOx films devices can be proved by the sudden drop of gate leakage, the negative differential resistance (NDR) phenomenon, the enhancement of IDS and sub-60 subthreshold swing. 5 nm ZrOx-based NCFETs achieve a clockwise hysteresis of 0.24 V, lower than 60 mV/decade SS and an 12% IDS enhancement compared to the control device without ZrOx. The suppressed NC effect of Al2O3/HfO2 NCFET compared with ZrOx NCFET is related to the partial switching of oxygen vacancy dipoles in the forward sweeping due to negative interfacial dipoles at the Al2O3/HfO2 interface.

Additional file 1. From the C–V curve of ZrOx NCFETs in Fig. S1 (a), we can see that the threshold voltage of the ZrOx NCFETs is around 0.5 V. From the XPS of TaN/ZrOx (4.2 nm)/Ge capacitors in Fig. S1 (b), we can see that a TaOx interfacial layer formed in the TaN/ZrOx interface and oxygen vacancies (ZrOx) in ZrOx because of the scavenging effect.

Here we report the ZrO2 - based Negative capacitance (NC) FETs with 45.06 mV/decade subthreshold swing (SS) under ±1 V V GS range, which can achieve new opportunities in furture voltage-scalable NCFET applications. The ferroelectric-like behavior of the Ge/ZrO2/TaN capacitors is proposed to be originated from the oxygen vacancy dipoles. The NC effect of the amorphous HfO2 and ZrO2 films devices can be proved by the sudden drop of gate leakage, the negative differential resistance (NDR) phenomenon, the enhancement of I DS and sub-60 subthreshold swing. 5 nm ZrO2 - based NCFETs achieve a clockwise hysteresis of of 0.24 V, lower than 60 mV/decade SS and an 12% I DS enhancement compared to the control device without ZrO2 . The suppressed NC effect of Al2O3/HfO2 NCFET compared with ZrO2 NCFET is related to the partical swiching of oxygen vacancy dipoles in the forward sweeping due to negative interfical dipoles at the Al2O3 /HfO2 interface.

In this letter, we experimentally investigate the impact of polarization ( ${P}$ ) switching behaviors on hysteretic and near hysteresis-free (NHF) negative capacitance field-effect transistors (NCFETs). Compared with the typical abrupt ${P}$ switching in hysteretic devices, NHF NCFETs show gradual and continuous response of ${P}$ under applied voltage, indicating that the mechanism underlying NHF characteristics is incomplete dipoles flipping, rather than complete dipoles switching. It has also been confirmed by a small amount of ${P}$ charge ( $0.1\sim 0.2 {\mu }\text{C}$ /cm2), which is still capable of achieving electrical performance improvement. This favors the device operation voltage scaling and reliability improvement for logic transistor applications.

We report the first investigation of the impacts of gate voltage sweep range ${V}_{\text {GS,range}}$ on the performance of negative capacitance (NC) transistors. As ${V}_{\text {GS,range}}$ is reduced, NC GeSn pFETs generally exhibit an increased hysteresis or a transition from non-hysteretic to hysteretic, and show a degradation of ${I}_{\text {DS}}$ . This is due to the reduction of the ratio of remnant polarization ${P}_{\text {r}}$ to coercive field ${E}_{\text {c}}$ with the reduced voltage across the HZO. Interestingly, however, some NC devices show a negligible impact of ${V}_{\text {GS,range}}$ on hysteresis and ${I}_{\text {DS}}$ . The NC transistor demonstrates a stable hysteresis in 139–149 mV range and the improved SS and ${I}_{\text {DS}}$ over the control device, with a reduced ${V}_{\text {GS,range}}$ of 0.5 to −0.5 V. To obtain device performance independent of ${V}_{\text {GS,range}}$ , the ratio of ${P}_{\text {r}}/{E}_{\text {c}}$ of the HZO needs to stabilize in a very small ${V}_{\text {GS,range}}$ .

We demonstrate negative capacitance (NC) Ge field-effect transistors (FETs) utilizing the TaN/HfZrO x /SiO2 gate stack. Typical characteristics of NC transistors, including the sub-60 mV/decade subthreshold swing (SS), the gate capacitance ${C} _{G}$ peak, and the negative differential resistance effect are achieved in NC Ge FETs without internal metal gate. Significant ${C} _{\textit {G}}$ peak, as the evidence of NC effect is obtained in NC transistors at the frequency up to MHz. Ferroelectric Ge FETs with counterclockwise ${I} _{\text {DS}} - {V} _{\text {GS}}$ loops due to trapping/detrapping, opposite hysteresis to the NC switching are also observed. The NC transistor has much steeper SS compared to the device dominated by the trapping/detrapping process. Statistical results show that only 10% of devices are dominated by the NC effect, and the density of defects in ferroelectric needs to be reduced to improve the yield of NC transistors.

We report the investigation of negative differential resistance (NDR) in negative capacitance (NC) germanium (Ge) pFETs. The NDR in NC transistors is attributed to the coupling of drain voltage to the internal gate voltage ${V}_{\text {int}}$ via the gate-to-drain capacitance. It is demonstrated that NDR strongly depends on the matching between the NC induced by ferroelectric capacitance ${C}_{\text {FE}}$ and the positive capacitance associated with the underlying transistor capacitance ${C}_{\text {MOS}}$ . For the non-hysteretic devices, NDR gets pronounced with an increased thickness of ferroelectric film ${t}_{\text {fe}}$ and ${V}_{\text {GS}}$ . This is attributed to the fact that the drain coupling factor is improved with an increased ${t}_{\text {fe}}$ and ${V}_{\text {GS}}$ , leading to the better matching between ${C}_{\text {FE}}$ and ${C}_{\text {MOS}}$ . For the hysteretic NC transistors, however, NDR is only obtained at the lower ${V}_{\text {GS}}$ , but not observed at higher ${V}_{\text {GS}}$ .

We report a comparative investigation of the negative capacitance (NC) Ge pFETs with different thicknesses of HfZrO x (HZO). Although the NC transistors with 6.6 nm HZO exhibit the sub-60 mV/decade subthreshold swing, the hysteresis inevitably occurs. The hysteresis-free characteristics are demonstrated in the NC Ge pFETs with 4.5 and 3.7 nm HZO. The influence of postannealing temperature on device performance is dependent on the thickness of HZO. With the postannealing at 450 °C, NC transistors with 4.5 and 3.7 nm HZO achieve 23% and 11% ${I}_{\textsf {DS}}$ improvement, respectively, over the control devices, at a ${V}_{\textsf {GS}}$ – ${V}_{\textsf {TH}}$ of −1.0 V and a ${V}_{\textsf {DS}}$ of –0.05 V. However, a higher postannealing temperature of 550 °C leads to the significant degradation in NC device with 4.5 nm HZO compared with the control device. It is further observed that, with the fixed HZO thickness and postannealing temperature, ${I}_{\textsf {DS}}$ of the NC Ge pFETs is improved as the ${C}_{G}$ peak gets increased.

We experimentally demonstrate that hysteresis of negative capacitance (NC) Ge pFETs is reduced through modulating the ferroelectric properties in HfZrOx (HZO) by changing the post annealing temperature. As annealing temperature varies from 350 °C to 450 °C, HZO exhibits a significant increasing in the ratio of remnant polarization Pr to coercive field Ec, which results in the improvement of the magnitude of ferroelectric NC CFE, therefore contributing to the reduction of hysteresis of the ferroelectric NC Ge transistors. It is also reported that the NC Ge transistor annealed at 450 °C has a small hysteresis of 0.10 V, and achieves the improved SS and IDS compared to control device without HZO.

In this work, we experimentally demonstrate comprehensively optimized anti-ferroelectric HfAlO x films, achieving high saturated polarization charge density and doping concentration in doped-HfO2 films. This allowed us to produce an ultrathin anti-ferroelectric energy storage device with high energy storage density (ESD). With the optimized deposition temperature of 300 °C, Hf:Al ratio of 18:1 and an electrode of tungsten, a 6.5 nm thick anti-ferroelectric HfAlO x film is realized with a high ESD of 63.7 J cm−3, which is the thinnest anti-ferroelectric film among all the reported works, associated with such a high ESD. This not only provides an effective way to improve the scaling ability of anti-ferroelectric HfAlO x films, but also demonstrates a new approach to strengthen the control of the phase transition.

We report a comparative study of the negative capacitance (NC) Ge pFETs with HfZrO x (HZO) partially and fully covering gate region. Utilizing the layout with HZO partially covering the gate, the internal voltage gain dV $_{{\textsf {int}}}$ / dV $_{{\textsf {GS}}} > \textsf {10}$ is demonstrated in NC Ge pFETs, which is attributed to the NC effect induced by HZO film. NC transistor demonstrates the hysteresis above 2 V, the sub-60 mV/decade subthreshold swing, and the improved drive current over internal-gated MOSFET. As the area of HZO is increased to fully cover the gate, the increased ferroelectric capacitance ${C} _{{\textsf {FE}}}$ produces the much better capacitance matching between ${C} _{\textsf {FE}}$ and the MOS capacitance of TaN/HfO2/Ge channel, contributing to the elimination of hysteresis of the NC Ge pFET. NC Ge pFETs with the gate fully covered by HZO achieve a much higher gate capacitance peak and a 36% enhancement in drive current compared to the devices with HZO partially covering gate.

Correlation of gate capacitance ${C} _{G}$ with drive current ${I} _{\textsf {DS}}$ and transconductance ${G} _{m}$ in negative capacitance (NC) Ge pFETs is first investigated. Hysteresis-free NC Ge pFETs integrated with 4.5-nm HZO achieving the improved ${I} _{\textsf {DS}}$ and ${G} _{m}$ over the control devices are fabricated. A peak in the ${C} _{G}$ versus gate voltage curve is demonstrated in the NC Ge pFET, indicating the NC effect induced by HZO film. It is observed that ${I} _{\textsf {DS}}$ and ${G} _{m}$ of the NC transistors are enhanced as the ${C} _{G}$ peak gets increased. This is attributed to the fact that, as the device operates in the NC region, both ${C} _{G}$ and internal gate voltage amplification are proportional to ${C} _{\textsf {FE}}$ /( ${C} _{\textsf {FE}}+{C}_{\textsf {MOS}}$ ), where ${C} _{\textsf {FE}}$ and ${C} _{\textsf {MOS}}$ are the NC of HZO and the MOS capacitance of the device, respectively.

Negative capacitance (NC) GeSn pFETs integrated with HfZrO x (HZO) ferroelectric film is demonstrated with sub-20 mV/decade subthreshold swing (SS) over two orders of magnitude of ${I}_{\text {DS}}$ . The ratio of remnant polarization to coercivity in HZO is significantly improved with the increasing of the annealing temperature from 400 °C to 500 °C, which contributes to the effective reduction of hysteresis in ferroelectric NC GeSn transistors. Ferroelectric NC GeSn pFET annealed at 500 °C achieves a hysteresis of 70 mV while maintaining a steep SS dramatically lower than 60 mV/decade, and an improved ${I}_{\text {DS}}$ over control device without HZO.

Additional file 1: Supplementary Information. Characterization of ferroelectric HZO substrate and more transfer curves of the HZO/MoS2 FeFET(PDF). Fig. S1 a Optical image of the MoS2/HZO FeFET. bPRphase and cPRampl of the HZO capacitor. XPS analysis of the 2 nm Al2O3/6 nm HZO/p+ Si shows pristine d Hf and e Zr peaks. f XPS depth profile of the Al2O3/HZO/p+ Si tri-layer structure. A top-view optic image of the HZO/MoS2 FeFET is shown in Fig. S1a. As shown in Fig. S1b and c, PRphase and PRampl of the HZO capacitor suggest ferroelectric behavior after 450 °C rapid thermal annealing (RTA) measured at 1kHz. As shown in Fig. S1d and e, the elemental and bond composition of HZO were examined by the X-ray photoelectron (XPS) measurements. Peaks are found to be 19.05 eV, 17.6 eV, 185.5 eV, and 183.2 eV, which correspond to the Hf 4f 5/2, Hf 4f 7/2, Zr 3d 3/2 and Zr 3d 5/2, respectively [27]. The atomic concentration along the depth profile in Fig. S1f further confirms the distribution of the Al2O3/HZO/p+ Si tri-layer structure. All the above confirm that the HZO film grown via our ALD system is highly crystalline. Fig. S2. Transfer curves of the HZO/MoS2 FeFET at increasing gate voltage (VGS) ranges with the linear y-axis. For a start, the transfer curves of the HZO/MoS2 FeFET under different back gate voltage sweep ranges (VGS,range) and different drain voltages (VDS) have been characterized in Fig. S2. It is demonstrated that, the counterclockwise hysteresis windows have been obtained at various gate voltage range (VGS,range) from (-5, 5V) to (-2, 2V). Simply, the mechanism underlying the hysteretic behaviors shown in the transfer curves during the bi-direction sweeping of VGS is threshold voltage shift, which can be modified by the effects of trapping/de-trapping [52] and polarization switching [53]. If the applied voltage is not high enough to switch the polarization in HZO film, charge trapping/de-trapping mechanism dominates and will cause clockwise hysteresis. The energy band at the interface between the MoS2 channel and ferroelectric back gate tends to bend downward after the positive back gate voltage. The more traps located below the Fermi-level; the more electrons are captured close to the interface. This will increase the threshold voltage after the positive gate pulse. The energy band at the interface between the MoS2 channel and ferroelectric back gate tends to bend upward after the negative back gate voltage. The more traps locate above the Fermi-level; the more electrons are released close to the interface. This will decrease the threshold voltage after the negative gate pulse [52]. If the applied voltage exceeds the coercive voltage in the HZO film, ferroelectric polarization mechanism dominates and will cause anti-clockwise hysteresis window [54–57]. Thus, it is easily concluded that the electrical performance of the device shown in Fig. S2 is dominated by ferroelectric switching. When the back-gate sweeps are in small ranges of 2V in Fig. S2a, we observed the nearly hysteresis-free switching. The hysteresis loops in Fig. S2b are counterclockwise for the back-gate sweep range of 6 V (from -3 V to 3 V). The minimum voltage under the drain is VGS – VDS = 2 V at VDS = 1 V, which should be larger than the coercive voltage Vc to switch the ferroelectric at the drain side. The estimated coercive voltage is consistent with Vc of 1.9 V when the maximum sweeping voltage is 3 V in Fig. 2a. When the applied voltage in HZO film exceeds +Vc, the ferroelectric polarization points into the MoS2 channel. Therefore, the electron charges in the MoS2 channel accumulate and the threshold voltage decreases. When the applied voltage in HZO film exceeds –Vc, the ferroelectric polarization points away from the MoS2 channel. Therefore, the electron charges in the MoS2 channel deplete and the threshold voltage increases. Nonetheless, we observed that the wider back-gate voltage range leads to larger counterclockwise hysteresis loops in Fig. S2c and d. Due to the increment of Vc in Fig. 2a with increasing applied voltage, the ferroelectric polarization switching in the HZO film can be enhanced with a larger shift in threshold voltage. Fig. S3 Transfer curves of the HZO/MoS2 FeFET on logarithmic scales with aVDS = 0.05 V, bVDS = 0.2 V, cVDS = 0.4 V. d Extracted back gate voltage VGS when drain current (IDS) equals to 70 nA with different VDS. Notably, besides the impact of VGS,range, it is found that VDS can definitely adjust the memory window as well, which requires a further investigation. The IDS-VGS curves on logarithmic scales under different VDS are characterized in Fig. S3. It is exhibited that, at a fixed VGS,range = (-2, 2 V), the values of VGS extracted at IDS = 70 nA for the bi-directional sweeping of VGS all shift towards the negative direction and the variation in forward sweeping of VGS is much more obvious over that of reverse sweeping, indicating the significant phenomena of negative drain induced barrier lowering (DIBL) [46, 58–61]. Generally, DIBL is a conventional short channel effect. With a short enough channel length, the increased VDS can easily pull down the barrier between source/drain and enable a negative shift of threshold voltage, which is the so called effect of DIBL. However, for a ferroelectric FeFET, an increased VDS is capable of producing a reduction of channel surface potential via the coupling between gate and drain induced by the parasitic capacitance between gate and drain (CGD), which means a positive shift of threshold voltage and can be called as negative DIBL.