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We fabricate, characterize, and establish the critical design criteria of Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify ${V}_{\textsf {TH}}$ shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and ${V}_{\textsf {TH}}$ shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 °C and endurance up to $5\times 10^{6}$ cycles initiated by the IL breakdown. Endurance up to 1012 cycles of partial polarization switching is shown in metal–FE–metal capacitor, in the absence of IL. A comprehensive metal–FE–insulator–semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance.

To reduce the power consumption in scaled CMOS integrated circuits, transistors operating at low supply voltage with steep subthreshold swing (SS) are highly desirable. The negative capacitance (NC) effect in ferroelectric materials has emerged as a possible solution for achieving steep SS in transistors. In order to effectively leverage this effect in device applications, a proper understanding of its time-dependent nature is crucial. Here, we demonstrate that the NC effect occurs within a time window which is bounded by the switching time of ferroelectric domains at the faster time limit and screening charge compensation time of polarization at the slower time limit. We study this temporal dynamics of NC effect both by performing the transient measurements of metal–ferroelectric hafnium zirconium oxide–insulator–semiconductor capacitor connected in series with a load resistor and by characterizing NC field-effect transistors (NCFETs) at different time scales. Our experimental results provide deeper insight into the understanding of NC effect, reveal the time dependent switching nature of NCFETs, and pave way for the advancement of steep-slope transistors technology.

The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar / pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (P r ) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark on-chip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.

The subthreshold swing (SS) in MOSFETs is limited to 60 mV/dec change in drain current at room temperature by the Boltzmanr distribution of carriers, thus limiting its operating voltage (V D >SS×log I on /I OFF ). Ferroelectric FETs can achieve sub-60 mV/dec by harnessing the negative capacitance (NC) effect in a Ferroelectric (FE) material, thus enabling low voltage operation [1]. Previous works have reported the direct observation of NC transients in Metal-FE-Metal (MFM) capacitors using epitaxial and polycrystalline ferroelectrics that are directly grown on metal electrodes [2][3][4]. For transistor application, however, FE directly grown on silicon channel with an interfacial oxide layer, such as the Metal-FE-Insulator-Semiconductor (MFIS), represent a more practica] configuration. In this paper, we report on the observation of negative capacitance transient for the first time in the Hafnium Zirconium oxide MFIS capacitor connected in series with a load resistor. We perform systematic experiments to study the influence of series resistance, applied AC voltage amplitude and the role of partial dipole switching on the NC effect.

We report, for the first time, a gate last process, used to fabricate Negative Capacitance field effect transistors (NCFETs) with Hf 0.5 Zr 0.5 O 2 (HZO) as ferroelectric (FE) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration. Long channel NCFET's with HZO thickness down to 5 nm exhibit consistent switching behavior with switching slope (SS rev ) below kT/q over four decades of drain current. Temperature dependent transport study shows that, the effective mobility of HZO NCFETs is 15 % higher than that of HfO 2 based control MOSFETs due to suppression of Hf diffusion into the interfacial SiO 2 layer (IL). Using the Preisach hysteresis model, which models dynamics of FE switching through a cluster of independent switching dipoles at arbitrary electric field, we (a) explain the asymmetric SS behavior of NCFETs in MFIS configuration, and (b) establish design guidelines for achieving sub-kT/q SS in both forward and reverse sweep direction.

Dense analog synaptic crossbar arrays are a promising candidate for neuromorphic hardware accelerators due to the ability to mitigate data movement by performing in-situ vector-matrix products and weight updates within the storage array itself. However, many analog weight storage cells suffer from long latencies or low dynamic ranges, limiting the achievable performance. In this work, we demonstrate that the voltage-controlled partial polarization switching dynamics in ferroelectric-field-effect transistors (FeFET) can be harnessed to enable a 32 state non-volatile analog synaptic weight cell with large dynamic range (67×) and low latency weight updates (50 ns) for an amplitude modulated pulse scheme.

This paper reports the first demonstration of a microwave-frequency operation of a GaAs MOSFET fabricated using a wet thermal oxidization of InAlP lattice-matched to GaAs to form a native-oxide gate insulator. Devices with 1-/spl mu/m gate lengths exhibit a cutoff frequency (f/sub t/) of 13.7 GHz and a maximum frequency of oscillation (f/sub max/) of 37.6 GHz, as well as a peak extrinsic transconductance of 73.6 mS/mm. A low-leakage current density of 3.8/spl times/10/sup -3/ A/cm/sup 2/ at 1-V bias for an MOS capacitor demonstrates the good insulating properties of the /spl sim/ 11-nm thick native gate oxide.

GaAs based MOSFETs have attracted significant interest as a potential technology for both digital and RF applications. Among many candidate gate insulating materials, the native oxide of InAlP offers a low leakage current and modest interface state density while at the same time being simple to fabricate and offering a path to low-cost devices. Both enhancement-mode and depletion-mode MOSFETs with gate lengths > 1 mum have been demonstrated with InAlP native oxide gate dielectrics. We present here the first sub-micron gate length InAlP native oxide GaAs-channel devices, with record microwave performance.

Extended abstract of a paper presented at Microscopy and Microanalysis 2006 in Chicago, Illinois, USA, July 30 – August 3, 2006