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A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient for programming data in the p-type GAA nanosheet TFT NVM because the GAA nanosheet structure enhances the source-to-drain component of the electric field in its channel. Therefore, the enhanced electric field of the BBHE phenomenon creates energetic electrons that surmount the tunneling oxide barrier easily and pass shallow traps in the charge trapping layer of the GAA TFT NVM. Consequently, the p-type GAA TFT NVM achieves low-voltage programming bias and satisfactory data retention

This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 108 because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.

The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable on/offcurrent ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an on/offcurrent ratio of 105 at W = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage Vth of the JL bulk FinFET can be easily tuned by varying substrate doping concentration Nsub. The modulation range of Vth as Nsub changes from 1018 to 1019 cm-3, which is around 30%.

The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.

In this study, we for the first time assess the characteristics and sensitivity of p-type junctionless (JL) gate-all around (GAA) nanowire transistor using 3D quantum transport device simulation for CMOS technology implementation. Since the doping concentration of p-type junctionless nanowire transistor does not as high as in n-type device due solid solubility of boron in silicon, it can be made by using midgap gate electrode material for appropriate threshold voltage. The p-type JLGAA transistor shows good on/off current ratio and better short channel characteristics compare to conventional inversion mode GAA structure. The sensitivity analyses show that the channel thickness affects the device performance such as threshold voltage (V th ), on current (I on ), and off current (I off ) significantly. In contrast, the channel length and oxide thickness have less impact owing to well control of short channel effect.

A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals have been successfully demonstrated. The process is simple and mask free. For the 3-nm-thick channel devices, the S.S. of 88 mV/dec and I on /I off ratio of more than 108 can be achieved. Extreme low applied voltage for band-to-band-tunneling-induced hot electron injection tunneling (BBHE) operation and excellent retention are proposed.

A novel method of fabricate ultrathin body (UTB) junctionless TFTs (JLTFT) with sub-10nm poly-Si channel has been successfully demonstrated. It is no additional mask for lithography. The cost of fabrication flow can be reduced by a novel method, that demonstrate at this work. UTB JLTFT has low threshold voltage and steep subthreshold slop 160 mV/dec at W/L=0.7um/1um. An ON/OFF current ratio is about 106, and transconductance does not decrease rapidly at a high drain voltage.

Multilevel resistance switching characteristics of the thin FeO x -transition layer were studies by controlling the maximum current compliance during set process. It is obtained that the LRS is mainly influenced by the compliance current value, which is nearly independent to the HRS. Moreover, statistics of set and reset electrical parameters show that the possible switching process is localized, and also, the multiple resistive switching states in the TiN/SiO 2 /FeO x /Fe memristor could be approved.

Multilevel resistance switching characteristics of the thin FeO x -transition layer were studies by controlling the maximum stopped voltage during reset process. It is obtained that the HRS is mainly influenced by the stopped voltage value, which is nearly independent to the LRS. Moreover, statistics of set and reset electrical parameters show that the possible switching process is localized, and also, the multiple resistive switching states in the TiN/SiO 2 /FeO x /Fe memristor could be approved.

We report the fabrication and characterization ofAlxGaixN pifl photodiodes (0.05 x 0.30) grown on sapphireby low-pressure metalorganic chemical vapor deposition. The devices present a visible-rejection of about four ordersofmagnitude with a cutoffwavelength that shifts from 350 nm to 291 nm. They also exhibit a constant responsivityfor five decades (30 mW/rn2 to 1 kW/m2) of optical power density. Using capacitance measurements, the values forthe acceptor concentration in the p-A1Ga1N region arid the unintentional donor concentration in the intrinsic regionare found. Photocurrent decays are exponential for high load resistances, with a time constant that corresponds tothe RC product ofthe system. For low load resistances the transient response becomes non-exponential, with a decaytime longer than the RC constant.Keywords: UV photodetectors, solar-blind, A1GaN, p-i-n photodetectors 1. INTRODUCTION High caliber ultraviolet (UV) and visible blind photodetectors are desired for many applications, both terrestrial andspace-based.' Notable progress in the device design, material quality and processing of wide bandgap 111-Nitridematerial, such as GaN and AlGa,N, has yielded visible-blind photodetectors with high responsivities, low darkcurrents, and fast response times,2'3 suitable for applications such as flame sensors, combustion process monitoring,and solar UV detection. While these visible-blind detectors can detect light at lower wavelengths and distinguish itfrom visible and infrared radiation, improvement is needed in the selectivity of the bandedge to more effectivelyfunction as a true solar-blind detector (?

In this work, double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device combines a new implant technology without using additional mask in standard 0.18 µm technology has been proposed and successfully fabricated. The breakdown voltage (BV) can be improved significantly with simply changing the implanted region length in this implant technology. Firstly, hydrodynamic transport simulations which analyze the high bias condition electric field distributions are examined to predict and explain the increase of breakdown voltage. Then the fabricated devices process flow is demonstrated, the structures are performed, and the breakdown voltages increase with different n-type double diffusion (NDD) photoresistor (PR) size using the change of PR exposure dose are investigated. The measurement results show that maximum NDD PR size achieves BV improvement of 6.3%, and 5% increase of figure of merit (FOM) evaluation. Throughout the whole fabrication process, no additional mask and device area show the potential of cost effective with the proposed technique. Such devices with good off-state breakdown voltage and specific on-resistance are very competitive with similar technologies and show good promising in system on chip (SOC) applications.

A 20 mm-wide enhancement-mode pseudomorphic high-electron-mobility transistor (E-PHEMT) has been developed. The device has high transconductance of 490 mS/mm, and high maximum drain current of 350 mA/mm due to the use of an Al0.3Ga0.7As/ In0.2Ga0.8As-based structure for carrier confinement. At 1.9 GHz and3.0 V, the E-PHEMT shows 34.1 dBm (128 mW/mm) output power with power-added efficiency (PAE) of 64.5%. At 2.4 V, the maximum saturated output power is 32.25 dBm and maximum PAE is 78.5%. The E-PHEMT demonstrates excellent power performance at 1.9 GHz and below 3 V.