Search

A low thermal budget (≤ 250 °C) chip-to-chip and chip-to-wafer three-dimensional (3D) integration of application-specific smaller artificial intelligence (AI) chips (2.5 mm × 2.5 mm) with 6 level metal (M#) layers were carried out by using TSV (Through – Si - Via) - last method. Several back-end-of-line processes were carefully optimized, such as multi-die thinning, M1 revealing, protection of revealed M1 during TSV metallization, die-level Cu-chemical mechanical polishing for re-distribution layer formation, and μ-bumping were carefully optimized. The diode parameter evaluation for the chips before and after 3D-integration revealed the successful fabrication of AI module for specific applications.

We propose a novel hybrid bonding technology with a high stacking yield using ultra-high density Cu nano-pillar (CNP) for exascale 2.5D/3D integration. To solve the critical issues of a current standard hybrid bonding technology, we developed scaled electrodes with slightly extruded structure and unique adhesive layer of anisotropic conductive film composed of ultra-high density CNP. Test element group (TEG) dies with 7-mm $\times 23$ -mm size are bonded to interposer wafer by a new hybrid bonding technology. Scaled electrodes with 3- $\mu \text{m}$ diameter and 6- $\mu \text{m}$ pitch are formed in each TEG chip. We confirmed for the first time that a huge number of electrodes of 4 309 200 are successfully connected in series with the joining yield of 100% due to the ultra-high density CNP.

A feasibility study was carried out for self-formation of metal wiring between LSI chips containing ultrafine-pitch Cu landing pads by employing a new concept of directed self-assembly (DSA) phenomena. Preliminary results suggest that it is highly feasible to electrically interconnect two LSI chips having Cu landing pads at 3μm pitch interval. Electrical contact between the flip-chip bonded dies was self-formed by dispersed Sn nano-dots in PS-b-PMMA (2:1) copolymer mixture after vacuum annealing at 280 °C.

The impacts of Cu contamination from a backside surface of a thinned wafer and Cu via on device reliabilities in 3-D IC integration are electrically evaluated. Intrinsic gettering (IG) layer, which was formed by high density oxygen precipitate, shows excellent Cu retardation characteristics from the backside surface of the thinned wafer. Extrinsic gettering (EG) layer, which was formed by postgrinded dry polish (DP) treatment shows good Cu retardation characteristics compared with other postgrinded treatments. The minimal 30-nm-thick Ta barrier layer in Cu via shows good barrier property to Cu diffusion from Cu via after annealing up to 60 min at 300 °C. However, it is not enough at 400 °C annealing, because the generation lifetime shows significant degradation after the initial annealing for 5 min. The DRAM cell characteristics show severe shortening retention time after an intentional Cu diffusion from the backside of the thinned DRAM chip at relatively low temperature of 300 °C.

With in the process temperature limit of less than 400 °C for via last technology, a simple method to improve the barrier ability of Ti layer in through Si via (TSV) has been studied. After annealing the TSV structures in vacuum at temperatures up to 400 °C, we did observe a tremendous improvement in leak current characteristics for SiO2 dielectric. It was found that the self-formed TiSi x at the interface between Cu and SiO 2 during the sputter deposition of Ti barrier layer was converted into an amorphous TiOx and SiOx upon vacuum annealing. This simple vacuum annealing of Cu-TSVs is a promising approach for using Ti as barrier layer in via-last 3D-integration.

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300oC annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300oC for 30min. As the annealing temperature increase higher than 400oC, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.

Suppressing leak current and blocking Cu diffusion into active Si from Cu through-silicon vias (TSVs) are important requirements for enhancing three-dimensional (3D) LSI performance and reliability. We have proposed and confirmed a cost effective means of enhancing the barrier property of sputtered Ti in high-aspect-ratio Cu-TSVs by simple vacuum annealing at 400 °C for 20 min. The self-formed amorphous TiSi2 at the interface between dielectric SiO2 (along the TSV side-wall) and barrier Ti layer is found to play a positive role in improving the leak current characteristics. As-formed TiSix was partially converted into TiO2 and SiO2 during the vacuum annealing above 200 °C, and nearly vanished after annealing at 400 °C. The immense importance of 400 °C vacuum-annealing is not only in terms of the improvement in the barrier characteristics of the Ti layer, but also it is being a prerequisite for preventing Cu popup in 3D-LSI. Both the X-ray photoelectron spectroscopy (XPS) and current–voltage (I–V) data clearly reveal that this simple vacuum annealing of Cu-TSVs at 400 °C has tremendous potential for implementation in cost-effective via-last 3D integration.

The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ~ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.

Reliability challenges in 3D LSI associated with mechanical constraints induced by Cu TSVs, μ-bumps and crystal defects, crystallinity in thinned Si wafer and metal contamination induced by Cu diffusion from TSVs and thinned backside surface are mainly discussed. Mechanical stresses induced by Cu TSVs and μ-bumps are strongly dependent on design rules and process parameters. DRAM retention characteristics were severely degraded by Si thinning, especially below 30 μm thickness. Minority carrier lifetime was seriously degraded by Cu diffusion from Cu TSVs as the blocking property of barrier layer in TSV is not sufficient. A dry polish (DP) treatment produced a superior extrinsic gettering (EG) layer to Cu diffusion at the backside. We suggest the nondestructive failure analysis using X-ray CT-scan to characterize TSVs connection and μ-bumps joining in 3D stacked LSIs.