Search

Current can cause electromigration (EM) damage in power device interconnects, thus the current density should be properly controlled. Lowering the current density requires placing and routing wide interconnects, increasing the die size. Therefore, enhanced EM entitlement would help to reduce the die size. Towards this goal, we have investigated the impact of strapped Cu interconnects on EM performance. The experiments show that the strapped layer can have $\sim 5\mathrm{X}$ EM lifetime than the separated layers when the strapping VIA distance is comparable to or shorter than the Blech length. The strapping metal layer not only provides shunting benefit but also improves the layer’s diffusion property. The strapping technique is simple and does not request special process changes, and provides enhanced current carrying capability needed for the advanced power devices with low on-resistance.

Design rules for specification of current densities in lines are driven by consideration of possible failure mechanisms. Under large amplitude intermittent current pulses, thermal stresses are the dominant cause for failure, with chief failure mechanisms being cyclic fatigue and plastic ratcheting of the metal line or dielectric fracture. In this study, a BEOL structure with aluminum or copper interconnects and silicon dioxide dielectric under well-separated current pulses is studied numerically through finite element simulations. The effects of varying duty cycles, peak current densities and line widths are studied. Line fatigue is found to be the dominant mode of failure in the absence of package structure. The results are characterized by the temperature rise in the line and the duty cycle of current pulses. A threshold is found to exist for the per cycle temperature rise below which there is no observable fatigue. A comparison of reliability between aluminum and copper lines is made and it is observed the copper lines permit a lower threshold temperature rise, but induce a lower dielectric stress. The results of the study may be used to develop peak current density specifications for dies.

Electromigration (EM) is a key limiting factor for designing lateral power devices. The metal interconnect for power devices features multiple fingers with strapped metal layers to carry large current, which leads to unique EM behaviors. In this paper, we present a new EM methodology for power device interconnects to account for these effects. The new model features circuit performance based failure criteria and allows more EM current limit for power devices with multiple fingers than the conventional rule. This provides relaxed EM rules for more efficient power device design.

Summary Convergent beam electron diffraction and geometric phase analysis were used to measure strain in the gate channel of a p-type strained silicon metal–oxide–semiconductor field-effect transistor. These measurements were made on exactly the same transmission electron microscopy specimen allowing for direct comparison of the relative advantages of each technique. The trends in the strain values show good agreement in both the [] and [001] directions, but the absolute strain values are offset from each other. This difference in the absolute strain measured using the two techniques is attributed to the way the reference strain is defined for each.

This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobility. A complete data analysis, including two different strain measurement techniques of nanobeam diffraction and geometric phase analysis, is presented, along with a quantitative understanding for each effect. It is reported that the eSiGe profile can have a significant impact on the STI proximity effect for p-MOSFETs and that DSL boundary proximity can cause significant channel mobility degradation for both n- and p-MOSFETs. Both effects result in the reduction in channel strain along the [110] direction.

An analysis of the effects of lens aberrations on the phase contrast images used for strain measurement by geometric phase analysis (GPA) in the TEM shows that errors may result when strain gradients are present and when [formula: see text] at the reciprocal lattice spacing used for the analysis. This conclusion is demonstrated experimentally using a model specimen consisting of a strained Si layer grown epitaxially on a Si-Ge alloy substrate. Image simulations for this model specimen show that strain gradients can introduce oscillations in strain maps when the defocus is not optimized for GPA. This work also makes it possible to identify other potential sources of error in GPA.

Electrostatic potentials within a core/shell nanowire structure, composed of an intrinsic germanium core surrounded by its oxide and a heavily doped germanium shell, were investigated by electron holographic analysis on its cross-section. The potential distribution resulting from interface charges as well as dopants was successfully imaged. The surface potential, screening length, and doping concentration for the heavily doped germanium shell were determined quantitatively from the potential image. These characteristics were compared with values obtained from a numerical solution of Poisson's equation.

This letter reports that geometric phase analysis of high-resolution images acquired in the high-angle annular darkfield scanning transmission electron microscopy can map strains at levels of accuracy and reproducibility needed for strained-silicon-device development. Two-dimensional strain maps were reconstructed for a p-type metal-oxide-semiconductor device which was strain-engineered using a recessed source and drain. This metrology provides sufficiently practical and reproducible local-strain tensors which can be measured on a routine basis. The techniques demonstrated here are informative for process development and failure analysis in the semiconductor industry.

Since strain engineering plays a key role in semiconductor technology development, a reliable and reproducible technique to measure local strain in devices is necessary for process development and failure analysis. In this paper, geometric phase analysis of high angle annular dark field - scanning transmission electron microscope images is presented as an effective technique to measure local strains in the current node of Si based transistors.

Extended abstract of a paper presented at Microscopy and Microanalysis 2012 in Phoenix, Arizona, USA, July 29 – August 2, 2012.

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

Extended abstract of a paper presented at Microscopy and Microanalysis 2008 in Albuquerque, New Mexico, USA, August 3 – August 7, 2008

Extended abstract of a paper presented at Microscopy and Microanalysis 2008 in Albuquerque, New Mexico, USA, August 3 – August 7, 2008

Extended abstract of a paper presented at Microscopy and Microanalysis 2004 in Savannah, Georgia, USA, August 1–5, 2004.

The distribution of breakdown times of thin film dielectrics, stressed in a constant voltage mode, is generally interpreted in terms of percolation theory of dielectric breakdown. The percolation model suggests that relative distribution of failure times (normalized to the mean) should narrow down considerably for thicker dielectrics. Explicitly contradicting this prediction, we find a larger distribution of failure times even for relatively thick polycrystalline oxides. We use atomic force microscopy and conductive AFM measurements to confirm that breakdown in these films are primarily localized in the grain boundaries, decorated with large number of pre-existing defects. The classical percolation model—adapted to this specific situation of spatially localized trap generation—offers an intuitive explanation of the breadth of the failure time distribution in thick polycrystalline dielectric. The theory offers an opportunity to optimize the intrinsic trade-off between variability and reliability in polycry...

Local strains in the channel and source/drain (S/D) of an advanced complementary metal-oxide-semiconductor device were measured by the geometric phase analysis applied to high resolution transmission electron microscope images. Two-dimensional strain maps were reconstructed for a 45nm p-type metal-oxide-semiconductor device which was strain-engineered using a recessed Si0.82Ge0.18 S/D. Lateral strains were uniform across the channel but vertical strains were found to vary considerably in the channel. Measured strains were used to estimate stresses and hole mobility enhancements.

Relaxation of strain by a partial dislocation and stacking fault in a strained Si film was characterized using geometric phase analysis of high-resolution transmission electron microscope (HRTEM) images. Movement of a 60° glide dislocation from the free surface to the film-substrate interface created a complex state of strain in the film. HRTEM image analysis was used to produce a quantitative measure of the atomic displacement fields that could be used as input to finite-element simulations of stress distributions and resulting affects on band structures.

Phase profiles within core-shell nanowires composed of intrinsic germanium cores and shells of germanium oxide and/or doped germanium were imaged using electron holography in a transmission electron microscope. Accurate mean inner potentials for germanium and its oxide were determined from phase data obtained from experimental electron holography with knowledge of the thickness profile of the nanowire. Using measured and simulated phase profiles, it was possible to determine the dopant concentration within a shell of doped germanium around an intrinsic germanium core. Measurement of mean inner potentials and dopant levels within semiconductor core-shell nanowires was demonstrated.

The effects of Ta barrier thickness on electromigration reliability of dual-damascene Cu/porous methylsilsesquioxane interconnects were investigated. With decreasing Ta barrier thicknesses, the threshold product of current density and line length (jL)c was found to be reduced due to less structural confinement from thinner barriers. The effect can be accounted for by the effective modulus of the structure except for the 75-A Ta barrier where the (jL)c product is reduced more than expected, probably due to the presence of defects in the barrier. Results from the early failure test structures revealed a bimodal failure distribution for samples with the 75-A and l00-A barriers. Focused ion beam microprobe and transmission electron microscopy observations revealed that the weak-mode early failure was caused by Cu outdiffusion through structural defects in the thin Ta barrier.