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In this work, we study and characterize the layout-induced device strain and its impact on RF performance of 22-nm-ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FDSOI) P-channel field-effect transistor (PFET). This will help in boosting and optimizing the RF performance for the targeted application. With shrinking device dimensions, conventional stress liners and embedded stressors used in strain-engineered CMOS devices become less effective. Therefore, intrinsically strained materials, such as compressively strained SiGe, are widely used to boost the holes’ mobility in the channel. The stress level depends on both the manufacturing process and device geometry, and the optimization of these leads to improved dc and RF performances of PFET devices. We hereby study various layout parameters, such as width and length of the active region, contacted poly pitch, number of fingers, and source/drain contact, to maximize the channel uniaxial strain parallel to the current flow direction and, thus, improve the electrical performances. The studied layout parameters are then applied on sliced-active (RX) structures, which enables to achieve up to 30% improvement of both ${f}_{T}$ and ${f}_{\text {MAX}}$ parameters of SiGe PFET with respect to a reference device. This also allows reducing the parasitic capacitance without significantly degrading the dc performance. The device strain modeling and physical characterization were conducted through the finite-element method (FEM) and nanobeam electron diffraction (NBED) in the transmission electron microscopy (TEM), respectively.

Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed ${g}_{\text {m}}/ {I}_{\text {D}}$ method with a revised form of the ${k}$ -sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of ${2}\,\,\cdot \,\,{10}^{{11}}\,\,\text {cm}^{-{2}}\text {eV}^{-{1}}$ . Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.

To meet the rising demand for Random Telegraph Noise (RTN) analysis, a new method to quickly separate RTN impacted devices from devices that show no RTN has been proposed and validated via existing analysis methods.

In this work buried channel devices were successfully integrated in HKMG. Analog, noise and reliability performance have been reported and compared to a surface device. The devices were processed to have the same V Tsat for the nominal geometry of a corresponding surface device. Advantages and drawbacks of the two integrations are discussed and explained with the support of calibrated TCAD simulations.

An improved set of Scribe Line Monitors (SLMs) with high device densities have been designed for inline monitoring of Random Telegraph Noise (RTN) and transistor local mismatch. This infrastructure offers increased statistics from measurement on a single wafer with parallel Device Under Test (DUT) testing capability thereby having an efficient testing time. The characterization results from engineering silicon are presented in this paper.

This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX®. The f MAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.

A new test methodology for the transit frequency f T and the maximum oscillation frequency I max has been developed. The novel measurement setup is optimized for high volume extraction enabling statistical analysis of both f T and I max in a small time frame. The functionality of this setup has been tested on advanced FDSOI transistors. Additionally, Monte-Carlo-Simulations were employed to evaluate the upper and lower boundaries for potential measurement errors.

A comparison of CMOS devices with best in class noise behavior and low power consumption for analog/mixed signal applications has been achieved by extensive TCAD simulations. The intrinsic gain gm/ID of FDSOI transistors was optimized by several process adjustments. An advanced bulk device with improved noise behavior was used as a reference and different bias conditions were simulated. With certain layer optimizations the gm/ID was improved by 50% in the low power regime. An additional improvement up to 50% has been achieved by biasing the FDSOI device in double gate mode (DGM).

The impact of device geometry, process integration and back bias on Low-Frequency Noise (LFN) performance of 22FDX® thin oxide devices has been investigated. Calibrated TCAD simulations were used to clarify the role of carrier distribution on LFN. More than 20% (30%) gate bias power spectrum density S Vg reduction is demonstrated in thin (thick) oxide devices with an appropriate choice of device construction and bias.

In this work we revisited the 22nm FDSOI technology for lowest power IoT, RF and mmWave applications. Ultra-low leakage and power devices are described, as part of the 22FDX® portfolio. Transistors performance is presented. N-FET (p-FET) drive current of 910μA/μm (856μA/μm) at 0.8V and 100pA/μm Ioff are reported fulfilling the requirements for ultra-low power and leakage design space. Excellent low noise is shown due to the suppressed RDF coming from the un-doped silicon channel. Superior fT and fmax have been measured on CMOS and LDMOS devices. 347GHz n-FET fT and 371GHz fmax were achieved on thin oxide CMOS devices. Simple PA circuit results are reported to highlight the benefit of 22FDX® technology for RF and mmWave applications. In conclusion, an outlook of the scalability as well as novel process integrations are discussed.

We report for the first time the implementation of SiGe buried stressors in a foundry production process at 28 nm and the observation of an additional benefit of improved short channel behavior (reduced DIBL) that results in at least 15% improvement in Idlin-Ioff independent of any benefit obtained from tensile strain. For RF applications, fT is projected to improve by at least 40% in n-MOSFETs with SiGe buried stressor.

We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (V T -flavors) within a cell. It is successfully applied with nMOS Low-V T (LVT) and pMOS Super-Low-V T (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted Silicon-On-Insulator (FDSOI) LETI standard cells using diffusion breaks. It enables adjusting the V T of pMOS subject to SiGe-channel-induced Local Layout Effect (LLE); leading experimentally to a 23% frequency gain on 22nm FDSOI technology for a 2-finger inverter Ring Oscillator (IVSX2 RO) vs. reference LVT at the same static leakage and V DD =0.4V supply voltage; which corresponds to the Minimum Energy Point (MEP). This solution is combined with Forward Body Biasing (FBB), which brings +253% frequency at V DD =0.4V and FBB=1.6V and improves the energy efficiency with a −13% minimum Energy Delay Product (EDP) along with a 50mV V DD reduction at the minimum EDP.

The 22FDX platform offered by GLOBALFOUNDRIES consists of a family of differentiated products architected to enable applications across a variety of market segments such as RF & Analog, Ultra-low Power (ULP), and Ultra-low Leakage (ULL). In order to ensure the successful development of these new products, as well as to meet the time-to-market constraints, predictive Technology Computer Aided Design (TCAD) tools have been extensively used to guide development efforts, narrow the experimental conditions and reduce the number of learning cycles. The areas of impact expanded to not only predicting device outcome from process input, but also to topics traditionally not addressed by TCAD. In this paper, we present a comprehensive TCAD that has been deployed to optimize core oxide transistors, define approaches to attain ULL targets, and simultaneously investigate the AC behavior at lower operating voltages while improving RF performance. The all-encompassing co-optimization of process, device and layout has been achieved within the same platform.

22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V min for 8T logic libraries, as well as 0.62V and 0.52V V min for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I off , and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f T /f MAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f MAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.

A major challenge for the application of strain engineering to enhance the performance of electronic devices is the quantification of strain on the nanoscale. Besides other techniques (Raman spectroscopy, X-ray diffraction) electron beam techniques allow strain analyses with a spatial resolution of a few nanometers and a reasonable strain sensitivity of 1x10 -3 (relative to the lattice constant of silicon). In the present work, we address practical issues in the application of nano-beam electron diffraction (NBED) to probe the strain in strained silicon layers and sub-100 nm structures. The investigated specimens were prepared on biaxially tensile strained silicon-on- insulator substrates with an initial strain of = 0.6% or 0.8%. Results of the NBED experiments were compared to data obtained by other strain measurement techniques; amongst them the strain mapping by peak-pairs analysis of high-angle annular dark field (HAADF) images was especially considered. NBED can be easily performed by use of STEM with a small aperture of the 2 nd condenser lens in the micro- or nanoprobe mode. The NBED principle consists in illuminating a nanometer-sized area of the specimen (being in zone axis orientation) with a nearly parallel electron beam and acquiring series of diffraction patterns at points along previously defined lines. The strain components of interest are generally calculated using a dedicated software package which is based on procedures for the analysis of electron diffraction patterns. The spatial resolution of NBED is determined by the beam diameter to a few nanometers. The

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

Continues innovation and over-scaling will keep the current SoC's scaling near the historic Moore's Law trend. 3D-TSVs and inductive coupling as well as proper partitioning will allow the opportunity to beat Moore's Law in the next technology nodes.

Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET ID,SAT = 870μA/μm and PFET ID,SAT = 465μA/μm at IOFF = 1nA/μm and VDS = 1V can be demonstrated by using compressive and tensile contact layers on (100)/ substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.

Within the semiconductor industry pure leading edge foundries serve a special mission by delivering state-of-the-art competitive logic performance with a strong focus on system-on-chip (SoC). Therefore they have to support a broad portfolio of different technology options on each node and GLOBALFOUNDRIES is an industry leader by representing this particular business model. It was formed out of AMD's manufacturing unit as well as Chartered Semiconductor Manufacturing. Both sides have a long time experience in leading-edge semiconductor manufacturing and technology capabilities one particular on silicon on insulator (SOI) based high performance microprocessors. To achieve the “high performance per watt” figure of merit technology elements like PD-SOI, strained-Si, an aggressive junction scaling as well as HKMG is needed together with an efficient multiple core- and power-efficient design. Those technology elements were developed and optimized for multiple generations beginning from an 180nm to a 32/28nm technology (Tab. 1).

This 3-D TCAD study demonstrates a new stress element by strained isolation oxide for Tri-Gate and similar FinFET structures. The simulation shows an uniform improvement of N- and PMOS drive current (10 %) by using a tensile strained isolation material between the fins processed on standard (100) bulk wafer with channel direction. Therefore it is a simple low-cost stress method for Tri-Gate and FinFET structures of 22nm technologies and beyond. The main stress direction is located along the channel width with a maximum near the pn-junctions. The stress effect can be improved further with reduced gate length which shows the compatibility of strained isolation oxide to future transistor generations.

Leading edge foundries need to fulfill a wide range of customer needs and have to deliver state-of-the-art performance processes. Therefore, an innovative but flexible modular technology set up is essential. This paper will show after a brief introduction of foundry challenges in general Global Foundries path towards the 28nm technology. Here, two key elements like high k metal gate process and embedded stressors are discussed. The article is concluded with an outlook on future device scaling from a leading edge foundry’s perspective. This look ahead includes recent transistor architecture and process technology trends. More specifically, some challenges of the 20nm technology are discussed. This node will push planar transistor technology to its physical limits. Due to this, subsequent nodes will require substantial innovations in process architecture and device concepts. Two potential device paths are foreseen and compared, i.e. FinFet and ET-SOI-UTBB devices.

We present an overview of partially-depleted silicon-on-insulator (PD-SOI) CMOS transistor technologies for high-performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD-SOI, strained Si, aggressive junction scaling, and asymmetric devices need hand-in-hand development with multiple-core and power-efficient designs. These techniques have been developed, applied, and optimized for 45nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, high-K metal-gate (HKMG) technology is key. Gate-first and replacement-gate HKMG integration as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

The impact of HCI and NBTI on device DC, Ring Oscillator (RO) AC as well as on the degradation of product operating frequency (F MAX ) has been extensively studied. We have developed a method, which allows the compensation of HCI/NBTI-related device and product performance degradation by adaptive control of operating voltage and power for the integrated circuit. Depending on the constraints applied to the product reliability and power, full or partial performance compensation is possible applying our new approach. The win in guard bands and thus a product classification advantage is demonstrated on one of our high-performance microprocessors.

In this paper we present, an overview of partial depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power efficient designs. These techniques have been developed, applied and optimized for 65/45nm volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, High K Metal Gate (HKMG) technology is key. Different HKMG integrations as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

Sub-40 nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12% and 10%, respectively, resulting in performance at 1.0 V and 100 nA/mum IOFF of NIDSAT=1354 muA/mum and PIDSAT=857 muA/mum. Product-level implementation of asymmetric transistors showed a speed benefit of 12%, at matched yield and improved reliability.

The influence of line edge and gate interface roughness on SOI-MOSFET performance is studied by simulation. Both types of roughness were implemented in the device simulator SIMBA through the Fourier synthesis approach and the simulations were performed with the drift diffusion and the quantum drift diffusion models. Scaled transistors showed more sensitivity to rough interfaces with shallow junctions.

Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent of the crystalline state of the Si. Both improve NMOS drive current, and the resulting improvements are additive to >27% NMOS IDSAT improvement. The first phenomenon is previously unreported. It has been identified to be localized in the source/drains, and yields more improvement with multiple offset implantation prior to capping and annealing.

The influence of technological parameters on the capacitive gate insulator thickness and the electrical transistor behavior of different technology nodes were simulated. Starting from calibrated PD- SOI-Transistors, designed for the 130 nm technology, scaled 45 nm technology transistors were examined. The inverter propagation delay time and corresponding saturation drive currents of different technologies with varying gate insulator thicknesses were compared under the aspect of manufacturability. Further improvements due to the implementation of metal gates were estimated.

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