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Graphene epitaxy on the Si face of a SiC wafer offers monolayer graphene with unique crystal orientation at the wafer-scale. However, due to carrier scattering near vicinal steps and excess bilayer stripes, the size of electrically uniform domains is limited to the width of the terraces extending up to a few microns. Nevertheless, the origin of carrier scattering at the SiC vicinal steps has not been clarified so far. A layer-resolved graphene transfer (LRGT) technique enables exfoliation of the epitaxial graphene formed on SiC wafers and transfer to flat Si wafers, which prepares crystallographically single-crystalline monolayer graphene. Because the LRGT flattens the deformed graphene at the terrace edges and permits an access to the graphene formed at the side wall of vicinal steps, components that affect the mobility of graphene formed near the vicinal steps of SiC could be individually investigated. Here, we reveal that the graphene formed at the side walls of step edges is pristine, and scattering near the steps is mainly attributed by the deformation of graphene at step edges of vicinalized SiC while partially from stripes of bilayer graphene. This study suggests that the two-step LRGT can prepare electrically single-domain graphene at the wafer-scale by removing the major possible sources of electrical degradation.

Information security underpins many aspects of modern society. However, silicon chips are vulnerable to hazards such as counterfeiting, tampering and information leakage through side-channel attacks (for example, by measuring power consumption, timing or electromagnetic radiation). Single-walled carbon nanotubes are a potential replacement for silicon as the channel material of transistors due to their superb electrical properties and intrinsic ultrathin body, but problems such as limited semiconducting purity and non-ideal assembly still need to be addressed before they can deliver high-performance electronics. Here, we show that by using these inherent imperfections, an unclonable electronic random structure can be constructed at low cost from carbon nanotubes. The nanotubes are self-assembled into patterned HfO2 trenches using ion-exchange chemistry, and the width of the trench is optimized to maximize the randomness of the nanotube placement. With this approach, two-dimensional (2D) random bit arrays are created that can offer ternary-bit architecture by determining the connection yield and switching type of the nanotube devices. As a result, our cryptographic keys provide a significantly higher level of security than conventional binary-bit architecture with the same key size.

High-performance logic based on carbon nanotubes (CNTs) requires high-density arrays of selectively placed semiconducting CNTs. Although polymer-wrapping methods can allow CNTs to be sorted to a >99.9% semiconducting purity, patterning these polymer-wrapped CNTs is an outstanding problem. We report the directed self-assembly of polymer-coated semiconducting CNTs using self-assembled monolayers that bind CNTs into arrays of patterned trenches. We demonstrate that CNTs can be placed into 100 nm wide HfO2 trenches with an electrical connection yield as high as 90% and into 50 nm wide trenches with a yield as high as 70%. Our directed self-assembly method is an important step forward in pitch scaling.

It is now widely recognized that continued performance gains in electronic computing will require new materials, both in the short and long term. In the short term, the silicon channel in transistors will be replaced by materials with higher mobility that are easier to “scale” (make thinner). In data storage, the goal is to have fast, non-volatile memory with a smaller cell size. In the long term, new architectures and new types of logic devices will be needed in order to further reduce power consumption. New materials cannot only boost performance, but can also add new functionalities, such as on-chip photonics, which can vastly improve interchip interconnects. The need for new materials is a big opportunity for materials research, but also a challenge. Replacement technologies must outperform conventional silicon technology, but also be compatible with the vast infrastructure of silicon manufacturing. Examples of some of the materials advances in the areas of computation, memory, and communication are given in this issue of MRS Bulletin.

High-performance, CMOS-compatible ring-oscillators based on carbon nanotubes are fabricated by scalable and fully manufacturable processes. As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond1,2. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

Carbon nanotubes have potential in the development of high-speed and power-efficient logic applications. However, for such technologies to be viable, a high density of semiconducting nanotubes must be placed at precise locations on a substrate. Here, we show that ion-exchange chemistry can be used to fabricate arrays of individually positioned carbon nanotubes with a density as high as 1 × 10(9) cm(-2)-two orders of magnitude higher than previous reports. With this approach, we assembled a high density of carbon-nanotube transistors in a conventional semiconductor fabrication line and then electrically tested more than 10,000 devices in a single chip. The ability to characterize such large distributions of nanotube devices is crucial for analysing transistor performance, yield and semiconducting nanotube purity.

The use of a UV-sensitive self-assembled monolayer photoresist to selectively deposit single-walled carbon nanotubes from solution using heterogeneous surface wettability is reported. This process combines ubiquitous photopatterning techniques with simple solution processing to yield highly selective and densely packed carbon nanotube patterns. The key mechanism is the change in surface chemistry caused by the UV-induced monolayer reaction. Selective deposition of carbon nanotubes was achieved by drop-casting the CNT solution onto the photopatterned substrates where the CNT solution only wets the exposed areas. Several compounds were employed, each with unique end groups that yield a range of surface energies. The selectivity is dependent on the contrast in the surface wettability. Increased selectivity was achieved by tuning the surface energy with addition of alcohol or a nonionic surfactant.

We describe a new design for an aberration-corrected low energy electron microscope (LEEM) and photo electron emission microscope (PEEM), equipped with an in-line electron energy filter. The chromatic and spherical aberrations of the objective lens are corrected with an electrostatic electron mirror that provides independent control over the chromatic and spherical aberration coefficients C(c) and C(3), as well as the mirror focal length, to match and correct the aberrations of the objective lens. For LEEM (PEEM) the theoretical resolution is calculated to be approximately 1.5 nm (approximately 4 nm). Unlike previous designs, this instrument makes use of two magnetic prism arrays to guide the electron beam from the sample to the electron mirror, removing chromatic dispersion in front of the mirror by symmetry. The aberration correction optics was retrofitted to an uncorrected instrument with a base resolution of 4.1 nm in LEEM. Initial results in LEEM show an improvement in resolution to approximately 2 nm.

We measure the role of structural defects, including grain boundaries and step edges, in determining the electrical transport characteristics of polycrystalline graphene monolayers synthesized on C-face SiC(0 0 0 ) by thermal decomposition. A combination of multi-probe scanning tunneling microscopy/potentiometry and low-energy electron microscopy allows the transport properties of individual grain boundaries to be correlated with their misorientation and atomic-level structure, without any device fabrication. We find that different types of grain boundary show dramatically different transport properties, and that boundaries can change structure and resistivity along their length. Boundary regions made up of dislocation superlattices separated by continuous graphene exhibit relatively low resistivity which is comparable to the resistivity of the graphene sheet itself. Other grain boundaries display trench structures with a resistivity 1–2 orders of magnitude greater and sufficient to dominate transport through the polycrystalline sheet. We also measure the transport properties of step edges and monolayer-bilayer boundaries on C-face graphene and compare them to Si-face graphene. Such measurements offer a guideline for optimizing graphene growth on SiC to improve its electronic properties.

We have used in situ low-energy electron microscopy (LEEM) to correlate the atomic and electronic structure of graphene films on polycrystalline Ni with nm-scale spatial resolution. Spatially resolved electron scattering measurements show that graphene monolayers formed by carbon segregation do not support the p-plasmon of graphene, indicating strong covalent bonding to the Ni. Graphene bilayers have the Bernal stacking characteristic of graphite and show the expected plasmon loss at 6.5 eV. The experimental results, in agreement with first-principles calculations, show that the p-band structure of free-standing graphene appears only in films with a thickness of at least two layers and demonstrate the sensitivity of the plasmon loss to the electronic structure.

We report the directed assembly of single-walled carbon nanotubes (SWCNTs) at lithographically defined positions on gate oxide surfaces, allowing for the high yield ( approximately 90%) and parallel fabrication of SWCNT device arrays. SWCNTs were first chemically functionalized through diazonium chemistry with a hydroxamic acid end group that both renders the SWCNTs water-soluble and discriminately binds the SWCNTs to basic metal oxide surfaces (i.e., hafnium oxide (HfO2)). The functionalized SWCNTs are then assembled from an aqueous solution into narrow trenches etched into SiO2 films with HfO2 at the bottom. The side walls of the patterned trenches induce alignment of the SWCNTs along the length of the trenches. Heating the structures to 600 degrees C removes the organic moieties, leaving pristine SWCNTs as evidenced by Raman spectroscopy and electrical measurements. Palladium source-drain electrodes deposited perpendicular to the trench length readily contact the ends of the aligned SWCNTs. The resultant devices exhibit the electrical performance expected for SWCNT devices, with no performance deterioration as a result of the placement process. This technique allows for the directed assembly and alignment of SWCNTs over a large area and results in a high yield of working devices, presenting a promising path toward large-scale SWCNT device integration.

▪ Abstract The use of low-energy electron microscopy (LEEM) to study reversible surface phase transitions is reviewed. Representative experiments are described that highlight the key advantages of LEEM: the ability to image surfaces in situ, at elevated temperature, with good spatial and temporal resolution. With these capabilities, the evolution of individual surface features—domains, facets, islands, steps, etc.—can be measured. Real-time and real-space imaging make LEEM a powerful tool for characterizing the thermodynamics and kinetics that govern surface phase transformations.

Nucleation and growth are often discussed in terms of kinetics, i.e. the adsorption of atoms from the gas phase or a solution onto a surface, the diffusion of these atoms on that surface, and their attachment to a growing nucleus, island or layer. In recent years, scanning tunneling and atomic force microscopy studies have tremendously improved our understanding of such kinetic processes for a wide range of materials. At relatively low temperatures where diffusion is slow, and where typical deposition rates result in adatom concentrations that far exceed the equilibrium concentration of adatoms on the surface, growth is indeed controlled by irreversible atomic scale kinetics. But at higher temperatures this is not necessarily the case. Indeed, the equilibrium concentration of adatoms can be so high that it is only slightly increased by an external flux. Diffusion can be so fast that spatially separated regions on the surface interact on a time scale that is not slow relative to the growth process. In such cases reversible, collective phenomena are more important than individual atomic events, and thermodynamics is more important than kinetics. In this paper we examine a number of cases related to nucleation and growth on surfaces, where a deep and quantitative insight into the growth process can be obtained by detailed consideration of the thermodynamics involved. It is our hope that this paper will help to bring about a balanced understanding of these phenomena, where kinetics and thermodynamics are two poles on a continuum with an importance that depends on the particulars of each experiment.

Using continuum elasticity theory, we investigate the stability of coexisting 7×7 and ‘1×1’ phases on Si(1 1 1) as a function of temperature. We find that of the many possible ‘droplet’ phases, a configuration in which triangular domains meet corner-to-side is the most stable. At fixed separation, the elastic interaction between two domains is minimized in the corner-to-side arrangement. Away from the transition temperature, the size of the domains decreases while the domain spacing diverges.

We observe the growth of crystalline SiC nanoparticles on Si(001) at 900 °C using in situ electron microscopy. Following nucleation and growth of the SiC, there is a massive migration of Si, forming a crystalline Si mound underneath each nanoparticle that lifts it 4–5 nm above the initial growth surface. The volume of the Si mounds is roughly five to seven times the volume of the SiC nanoparticles. We propose that relaxation of strain drives the mound formation. This new mechanism for relieving interfacial strain, which involves a dramatic restructuring of the substrate, is in striking contrast to the familiar scenario in which only the deposited material restructures to relieve strain.

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moore's law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling. This review examines the potential performance advantages of a CNT-based computing technology, outlines the remaining challenges, and describes the recent progress on these fronts. Although overcoming these issues will be challenging and will require a large, sustained effort from both industry and academia, the recent progress in the field is a cause for optimism that these materials can have an impact on future technologies.

Thin films of carbon nanotubes (CNTs) are fabricated from solution using a one-step directed assembly strategy. Very high surface selectivity and exceptionally high CNT densities can be observed in small features with complex shapes. This directed assembly technique makes use of minimum amounts of CNTs and low toxicity solvents, and can be applied to metallic, semiconducting and mixed CNTs for fabrication of thin films over macroscopic areas. The thin films obtained with this approach are used for thin-film transistor (TFT) fabrication, and their electrical characterization is described.

Experimental data on the decay rate of two-dimensional islands on Cu(100) as a function of temperature are reported. The decay is limited by the attachment-detachment process. A comparison of the experimentally observed activation energy for the decay rate with results from first-principles theory renders further support to the understanding that on Cu(100) island decay is due to mass transport via vacancies.

Silicon nanowires hold great promise as components of tiny electronic devices, but the usual method of growing them is poorly understood. New work shows that excessive cleanliness can actually stunt a nanowire's growth. They are made by the ‘vapour–liquid–solid’ method, in which a tiny liquid droplet of a metal such as gold absorbs silicon atoms from a gaseous precursor molecule. As the droplet saturates with silicon, it grows a solid, cylindrical silicon crystal whose diameter is determined by the size of the droplet. But in conditions of extreme cleanliness, gold atoms from the droplet can migrate over the surface of the growing nanowire, resulting in misshapen structures. Interest in nanowires continues to grow, fuelled in part by applications in nanotechnology1,2,3,4,5. The ability to engineer nanowire properties makes them especially promising in nanoelectronics6,7,8,9. Most silicon nanowires are grown using the vapour–liquid–solid (VLS) mechanism, in which the nanowire grows from a gold/silicon catalyst droplet during silicon chemical vapour deposition10,11,12,13. Despite over 40 years of study, many aspects of VLS growth are not well understood. For example, in the conventional picture the catalyst droplet does not change during growth, and the nanowire sidewalls consist of clean silicon facets10,11,12,13. Here we demonstrate that these assumptions are false for silicon nanowires grown on Si(111) under conditions where all of the experimental parameters (surface structure, gas cleanliness, and background contaminants) are carefully controlled. We show that gold diffusion during growth determines the length, shape, and sidewall properties of the nanowires. Gold from the catalyst droplets wets the nanowire sidewalls, eventually consuming the droplets and terminating VLS growth. Gold diffusion from the smaller droplets to the larger ones (Ostwald ripening) leads to nanowire diameters that change during growth. These results show that the silicon nanowire growth is fundamentally limited by gold diffusion: smooth, arbitrarily long nanowires cannot be grown without eliminating gold migration.

We have used scanning tunneling microscopy to study the Ostwald ripening of 2D islands of Cu grown on Cu(001). By considering the time dependence of the sizes of individual islands we have characterized the mechanisms for the ripening. Our result is unexpected for a simple metal surface: The flow of atoms from one island to another is limited by attachment-detachment kinetics at the island edges. To explain this result, we propose that the transport of atoms between islands occurs by vacancy, rather than by adatom, diffusion. {copyright} {ital 1997} {ital The American Physical Society}

Complementary logic gates based on chemically assisted directed assembly of solution carbon nanotubes with a high semiconducting purity (~91%) are demonstrated. Air stable, high quality carbon nanotube NFETs have been fabricated with low work function Erbium contacts, enabling an inverter gain of > 7 from transistors with 50 nm channel lengths. The substantial device yields of both NFET (~31%) and PFET (~44%) on the same chip allow us to construct and test a large number of CNT complementary logic gates for the first time. > 11% inverter yield from over 400 circuits tested along with fully functional NAND2 gates show promise of our fabrication scheme. This study points out several key directions for further yield enhancement, in which increasing the successful rate of CNT deposition into the trench plays a major role.

Monolayer Graphene via Two Transfers Oriented monolayers of graphene containing some bilayer regions can be formed on silicon carbide crystal surfaces, but, to be cost effective, the graphene needs to be exfoliated and transferred to other substrates so that the silicon carbide crystal can be reused. Kim et al. (p. 833 , published online 31 October) used a nickel film grown to a thickness designed to impart a particular surface stress as a “handle” to exfoliate the graphene layer for transfer to a silica substrate. An additional gold layer was then used to remove the excess monolayer from the bilayer regions to create a monolayer suitable for electronics applications.

Organic light-emitting diodes are emerging as leading technologies for both high quality display and lighting. However, the transparent conductive electrode used in the current organic light-emitting diode technologies increases the overall cost and has limited bendability for future flexible applications. Here we use single-layer graphene as an alternative flexible transparent conductor, yielding white organic light-emitting diodes with brightness and efficiency sufficient for general lighting. The performance improvement is attributed to the device structure, which allows direct hole injection from the single-layer graphene anode into the light-emitting layers, reducing carrier trapping induced efficiency roll-off. By employing a light out-coupling structure, phosphorescent green organic light-emitting diodes exhibit external quantum efficiency60%, while phosphorescent white organic light-emitting diodes exhibit external quantum efficiency45% at 10,000 cd m(-2) with colour rendering index of 85. The power efficiency of white organic light-emitting diodes reaches 80 lm W(-1) at 3,000 cd m(-2), comparable to the most efficient lighting technologies.

We have used low-energy electron microscopy to study atomic exchange between the bulk and the (111) surface of Pt above 1100 K. We find that the area of two-dimensional surface islands increases when the temperature is raised and decreases when the temperature is lowered, suggesting that thermal bulk vacancies are created at the surface. By measuring the temperature dependence of the change in area of the islands, we determine a Pt bulk vacancy formation energy of 1.54±0.07 eV, consistent with previous measurements and calculations.

The growth of graphene by catalytic decomposition of ethylene on Cu(111) in an ultra-high vacuum system was investigated with low energy electron diffraction, low energy electron microscopy, and atomic force microscopy. Attempts to form a graphene overlayer using ethylene at pressures as high as 10 mTorr and substrate temperatures as high as 900 $^\circ$C resulted in almost no graphene growth. By using an argon overpressure, the growth of epitaxial graphene on Cu(111) was achieved. The suppression of graphene growth without the use of an argon overpressure is attributed to Cu sublimation at elevated temperatures. During the initial stages of growth, a random distribution of rounded graphene islands is observed. The predominant rotational orientation of the islands is within $\pm1^\circ$ of the Cu(111) substrate lattice.

In Part I we described a new design for an aberration-corrected Low Energy Electron Microscope (LEEM) and Photo Electron Emission Microscope (PEEM) equipped with an in-line electron energy filter. The chromatic and spherical aberrations of the objective lens are corrected with an electrostatic electron mirror that provides independent control of the chromatic and spherical aberration coefficients Cc and C3, as well as the mirror focal length. In this Part II we discuss details of microscope operation, how the microscope is set up in a systematic fashion, and we present typical results.

Using the Si(111) surface as an example, we show how temperature can be used to tune the size of domains during a surface phase transition. From analysis of the measured stable domain sizes, we determine key material parameters and clarify the close relationship between nucleation and thermodynamic size selection. More generally, the model we developed describes nanoscale self-assembly processes in contact with a reservoir (for example, liquid- or vapor-phase epitaxy).

We present the first analysis of device yield and material composition for several low work-function metal contacts to carbon nanotubes (CNT), including the first demonstration of high-performance n-channel field-effect transistors (NFET) from erbium (Er) and lanthanum (La). Our results indicate drastic improvement in NFET yield by appropriate metal selection and optimization of deposition conditions.

The high carrier mobility of graphene is key to its applications, and understanding the factors that limit mobility is essential for future devices. Yet, despite significant progress, mobilities in excess of the 2×10(5) cm(2) V(-1) s(-1) demonstrated in free-standing graphene films have not been duplicated in conventional graphene devices fabricated on substrates. Understanding the origins of this degradation is perhaps the main challenge facing graphene device research. Experiments that probe carrier scattering in devices are often indirect, relying on the predictions of a specific model for scattering, such as random charged impurities in the substrate. Here, we describe model-independent, atomic-scale transport measurements that show that scattering at two key defects--surface steps and changes in layer thickness--seriously degrades transport in epitaxial graphene films on SiC. These measurements demonstrate the strong impact of atomic-scale substrate features on graphene performance.

We have determined the growth mode of graphene on SiC(0001) and $\mathrm{SiC}(000\overline{1})$ using ultrathin, isotopically labeled $\mathrm{Si}^{13}\mathrm{C}$ ``marker layers'' grown epitaxially on the $\mathrm{Si}^{12}\mathrm{C}$ surfaces. Few-layer graphene overlayers were formed via thermal decomposition at elevated temperature. For both surface terminations (Si face and C face), we find that the $^{13}\mathrm{C}$ is located mainly in the outermost graphene layers, indicating that, during decomposition, new graphene layers form underneath existing ones.

Graphene single crystals with dimensions of up to 0.5 mm on a side were grown by low-pressure chemical vapor deposition in copper-foil enclosures using methane as a precursor. Low-energy electron microscopy analysis showed that the large graphene domains had a single crystallographic orientation, with an occasional domain having two orientations. Raman spectroscopy revealed the graphene single crystals to be uniform monolayers with a low D-band intensity. The electron mobility of graphene films extracted from field-effect transistor measurements was found to be higher than 4000 cm(2) V(-1) s(-1) at room temperature.

Depth profiling of graphene with high-resolution ion beam analysis is a practical method for analysis of monolayer thicknesses of graphene. Not only is the energy resolution sufficient to resolve graphene from underlying SiC, but by use of isotope labeling it is possible to tag graphene generated from reacted ethylene. Furthermore, we are able to analyze graphene supported by oxidized Si(100) substrates, allowing the study of graphene films grown by chemical vapor deposition on metal and transfered to silicon. This introduces a powerful method to explore the fundamentals of graphene formation.

The authors report the results of a high-resolution Electron-Energy Loss Spectroscopy (EELS) investigation of Be(0001) surface. Two dispersive surface vibrational modes are observed in the {bar {Gamma}} to {bar M} direction: a sagittal-plane mode (the Rayleigh wave) and a shear horizontal mode. They have compared their experimental results to a 300-layer slab calculation and to a semi-infinite Green`s function calculation of Sameth and Mele. Compared with the experimental results, both calculations predict a higher energy for the Rayleigh wave and lower energy for the shear horizontal mode. These results are consistent with stronger in-plane bonding and weaker interplanar bonding at the surface, in accord with other theoretical predictions.

Graphene, a two-dimensional carbon form with the highest intrinsic carrier mobility and many desirable physical properties at room temperature, is considered a promising material for ultrahigh speed and low power devices with the possibility of strong scaling potential due to the ultra-thin body. (Fig. 1) [1–3] Here IBM reports progress in graphene nanoelectronics, synthesizing wafer-scale monolayer-controlled graphene and fabricating high-speed single atomic layer graphene FETs (GFET) with the highest value reported cut-off frequency (f T ) 50 GHz, exceeding that of the same gate length Si FETs. It is achieved by improving gate oxide deposition and reducing series resistance. Systematic characterization and small-signal models enable further engineering and optimization for even higher performance. The high I on /I off ratios from bi-layer graphene suggest potential not only for analog but also for logic applications.

When epitaxial graphene layers are formed on SiC(0001), the first carbon layer (known as the ``buffer layer''), while relatively easy to synthesize, does not have the desirable electrical properties of graphene. The conductivity is poor due to a disruption of the graphene $\ensuremath{\pi}$ bands by covalent bonding to the SiC substrate. Here we show that it is possible to restore the graphene $\ensuremath{\pi}$ bands by inserting a thin oxide layer between the buffer layer and SiC substrate using a low temperature, complementary metal-oxide semiconductor-compatible process that does not damage the graphene layer.

The effects of channel length scaling on carbon nanotube field-effect transistor (CNTFET) performance was investigated by varying device lengths on the same nanotube. Results show that scaling improves performance with substantial increases in on-current, resistances closer to the quantum limit than have ever been reported, and the shortest (∼30 nm) well-behaving CNTFETs to date.

Using in situ electron microscopy, we have measured the structure of $\mathrm{SiC}(0001)\mathrm{\text{\ensuremath{-}}}4H$ during annealing in vacuum. Above $1000\text{ }\ifmmode^\circ\else\textdegree\fi{}\mathrm{C}$, an additional SiC bilayer forms on the surface that changes the polytype from hexagonal ($4H$) to cubic ($3C$). The interaction with surface steps prevents the cubic layer from growing thicker: the new phase does not wet the steps of the underlying $4H$ substrate. Instead, the cubic layer expands laterally, accelerating step bunching in the surrounding hexagonal regions. During SiC homoepitaxy, this lack of step edge wetting leads to the growth of $3C$ twins separated by deep grooves.

We have studied the formation of graphene on the Si face of SiC(0001)-6H and -4H using in situ electron microscopy. By imaging the nucleation and growth of the $6\sqrt{3}$ ``buffer layer'' during annealing in vacuum we identify key factors responsible for the appearance of deep pits during graphene formation. Pits form because domains of the buffer layer pin decomposing surface steps. Graphene is observed to nucleate in the pits, where the step density is high.