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This article discusses topics in the field of business analysis, which is the basic element of the operation of modern organizations. The aim of this publication is to present and evaluate four selected tools for modeling business diagrams in BPMN notation. As part of the introduction to the topic, business processes were characterized, their analysis was defined, and the reader was introduced to the BPMN notation and the tested tools. The research methodology and its course were also defined. Then, the research was carried out in accordance with the adopted methodology. The conclusion of this work was the result of the research together with the analysis. Finally, the conducted experiments were summarized together with conclusions.

Diagnosis becomes a much more prevalent factor in the successful fabrication process of a design. In order to keep up with continuously shrinking technology nodes, compression along with compaction techniques became a standard methodology allowing to control the cost of test. Typically compaction techniques focus on detectability thus maintaining high quality of test, but neglect or, in many cases, ignore their impact on diagnosis. This paper presents a compactor which allows significantly improving chain diagnosis resolution while maintaining high quality standards from detectability point of view and having virtually no impact on test time and logic diagnosis. The paper presents the X-press compactor which is driven in a way allowing to maximize diagnostic ability of chain failures. Specifically, the number of physical failure analysis-ready cases increased up to two times. The feasibility and efficiency of the proposed solution is confirmed by a number of experimental results performed for industrial designs, including actual chain diagnosis.

O objetivo desta tese é encontrar as determinantes que afetam os preços das criptomoedas. Foram estudadas as quatro principais criptomoedas e suas determinantes, de acordo com a literatura, usando-se dados entre os anos de 2013 e 2018. Especificamente, usaram-se variáveis diretamente relacionadas com as criptomoedas, tal como volume de transacções, e variáveis relacionadas com o ambiente financeiro e económico, tal como o índice SP500. Utilizando-se especificações do tipo ARCH, estimaram-se cinco modelos - dois para Bitcoin usando dois tipos diferentes de modelos ARCH, e um para cada uma das outras três moedas, as quais podem ser denominadas "altcoins" (moedas alternativas ao Bitcoin). Foram encontradas relações significativas entre as determinantes identificadas pela recente literatura na área, por exemplo o dólar Americano, o Euro, o ouro, a prata, retornos dos mercados financeiros, e características dos mercados das criptomoedas em estudo. Em particular, concluiu-se que os retornos do dólar têm sempre uma relação negativa com os retornos das criptomoedas e que o valor das transações têm sempre uma relação positiva com os retornos das criptomoedas. Outros determinantes têm diferentes impactos (positivos ou negativos) dependendo da criptomoeda em análise. The purpose of this dissertation is to find determinants affecting the cryptocurrencies prices. We use the four main cryptocurrencies and their main determinants, according to the literature, using data between the years of 2013 and 2018. Specifically, we use variables directly related with cryptocurrencies, like generated cryptocurrencies, and variables related with the financial and economic environment, like the SP 500 index. By using ARCH-type specifications we estimated five models - two for Bitcoin using two different types of ARCH models, and one for each of three other coins, which are called altcoins (alternative coins for Bitcoin). We found significant relationships between the determinants uncovered by the recent literature on the subject, for example the USA dollar, the Eurozone Euro, gold, silver, returns in financial markets, and characteristics of cryptocurrencies markets and the four cryptocurrencies in study. In particular, we found that returns of the dollar have always a negative relationship with the returns of each cryptocurrencies and the dollar value of daily transactions has always a positive relationship with the returns of each cryptocurrency. Other determinants have different impacts (either negative or positive) depending on the analyzed cryptocurrency.

All Automatic Test Equipment (ATEs) have fail buffer capacity limit, and the limited amount of collected failure data during testing has big negative impact on scan chain diagnostic resolutions. In the past, adaptive pattern reordering algorithms were proposed to improve the scan chain diagnostic resolutions. However in reality, either many ATEs do not support the proposed adaptive testing flows without additional test cost or the test engineers do not know how to program the ATEs to implement the proposed adaptive testing flows. Therefore, as far as we know, all of prior proposed adaptive testing flows are not applied in the real world yet. In this paper, we propose a non-adaptive pattern reordering flow to improve the scan chain diagnostic resolution, which can be readily applied in the current manufacture testing and volume diagnosis environment.

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein.

The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA -- based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to test bandwidth management is demonstrated by running experiments on several industrial SoC designs and is reported herein.

Introduction. The aim of this study was to evaluate two measures in a cognitive examination: psychomotor function and the perception of time (PT) in patients after intravenous anesthesia for endoscopic procedures.Material and Methods. We tested 23 anesthetized patients (Anesthesia Group, AG) and 17 not anesthetized patients (Control Group, CG). The Dufour Cross-Shaped Apparatus (DA) was used to assess quick reactions. Perception of time (PT) was measured for 1-, 2-, 5-, and 7-second intervals. The tests were performed before the anesthesia was administered and 1.5, 3, and 6 hours after the procedure was completed.Results. The intervals that were generated and the reproduced visual stimuli were shorter than the patterns. The reproduced 1- and 2-second auditory stimuli were longer than the patterns. The remaining reproduced auditory impulses were shorter than the patterns.Conclusions. In anesthetized patients, quick psychomotor reactions and the ability to time intervals are preserved 1.5 h and later after intravenous anesthesia for endoscopy.

Growing test data volume and excessive test power consumption in at-speed scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power in atspeeddelay test utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results for a set of industrial circuits show that the proposed method, on average, reduces test data volume by a factor 2.7, switching activity during scan shift by a factor of 5 and peak switching activity during test response capture by a factor of 2.

The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.

Due to a production error, an incorrect figure was used for Fig. 8 on p. 1781 in the above paper (ibid., vol. 32, no. 11, pp. 1776-1786, Nov. 2013). The correct figure is presented here.