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This paper presents quantum dot channel (QDC) FETs in quantum wire and coupled quantum dot configurations for cryogenic operation with multi-state operation. It also describes gate-all-around (GAA) quantum dot channel (QDC) FETs that exhibit potential multi-state characteristics at room temperature. FETs with cladded Si and Ge quantum dot layers as a transport channel have been fabricated. The formation of a quantum dot superlattice (QDSL) when SiOx-cladded Si and/or GeOx-cladded Ge quantum dots (QD) are assembled results in mini-energy sub-bands in the conduction and valence band. The intra-mini-energy band transitions results in significant changes in the drain current when gate and/or drain voltages are varied. This novel feature provides a pathway for 16-/32-state logic in CMOS-X configuration. The gate-defined Si quantum dot FETs, comprising of tunnel barrier coupled, have been reported for quantum computing at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

This paper describes the fabrication of quantum dot gate (QDG) n -FETs using GeOx-cladded Ge quantum dot self-assembled on tunnel gate oxide. Experimental I–V characteristics exhibiting 4-states are presented. Simulations are presented for the operation of a viable 8-state SRAM using QDG-FETs. [ABSTRACT FROM AUTHOR]

Static random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM. Ternary, quaternary, and higher-order logic (MLV) systems have shown the potential in overcoming these limitations in increasing the information density compared to the traditional binary system. The quantum dot channel field-effect transistor (QDC-FET) and quantum well Spatial Wavefunction Switched field-effect transistor (SWS-FET) are a new alternative with multiple operating states, low power consumption, and smaller footprints. This work presents a new four-state SRAM design that uses SWS-FET and compares it with Voltage-Mode CMOS Quaternary logic design. In addition, this work studies the noise margin in the memory circuit of the quadrilateral logic system and its effect on data stability. Furthermore, this study shows the reliability of quaternary SRAM design by evaluating the impact of errors. [ABSTRACT FROM AUTHOR]

This paper aims to assess the power dissipation of a threshold quantizer (TIQ) 2-bit-based comparator using a SWS-FET-based inverter [1-2, 4-5]. Unlike conventional comparators, SWS-based comparator functionalized with TIQ comprises two or more vertically stacked quantum dots or well channels [1–3, 5-6]. Herein, power dissipation analysis of the simulated circuit is carried out using Cadence by integrating the Berkeley Short-Channel IGFET Model (BSIM) and the analog behavioral model (ABM) [1, 3-4, 9]. The transient behavior of the inverter circuit is evaluated using 180 nm technology node. Our results demonstrated a significant reduction in power dissipation which overcome the limitation of previous 4-state logic implementations. [ABSTRACT FROM AUTHOR]

This paper describes fabrication of Quantum Dot Gate n-FETs using SiOx-cladded Si quantum dot self-assembled on the tunnel gate oxide. Experimental I-V characteristics exhibiting 4-states are presented. Simulation is presented for the operation of viable 4-state SRAMs using QDG-FETs. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive analysis of power dissipation and propagation delay in 2-bit SRAM configurations ranging from 7T to 10T, building upon previous work on 6T 2-bit/4-state SWSFET SRAM designs. The study compares the performance of SWSFET SRAMs with CMOS-based 2-state SRAMs [7], highlighting the former's significant advantages in speed and power consumption. Utilizing Cadence simulations and models such as Analog Behavioral Model (ABM) and EKV (Enz–Krummenacher–Vittoz), the analysis incorporates real-world 0.18- μ m technology considerations. The research explores the design nuances of 7T–10T SRAM configurations using SWS-FETs, leveraging their unique characteristics like vertically stacked quantum well/quantum dot channels. Power dissipation analysis reveals varying trends across different SRAM configurations, with notable shifts in voltage changes during transitions. Similarly, propagation delay assessments showcase diverse durations for different voltage transitions, underscoring the impact of SRAM configuration changes on efficiency and complexity. In addition, parasitic capacitance is crucial for optimizing the performance, power efficiency, and reliability of SRAM cells. In these circuits an internal storage parasitic capacitance of 1 fF has been considered to evaluate its effects through simulation-based analysis during the memory cell design process. The findings contribute valuable insights into the trade-offs involved in SRAM design, particularly concerning power dissipation and propagation delay, and are presented. Overall, this study sheds light on the promising potential of SWS-FETs for enhancing memory circuitry performance. [ABSTRACT FROM AUTHOR]

This paper presents the characterization and testing of electrochemical sensor using microfluidic system. Various geometric patterns were laser cut into the platinum working electrode of a biosensor. In this work, a microfluidic chamber was designed that allows phosphate buffer solution (PBS) to flow across the sensor, using a peristaltic pump, while varying the concentration of hydrogen peroxide. The amperometric characterization of the electrochemical sensor with 25, 50, 75, and 100 μ m perforation and 75 μ m spacing showed the highest sensitivity. This result was to be expected the purpose of patterning the sensors was to provide a 3-dimensional structure to the planar electrode in order for the enzyme, glucose oxidase, to be immobilized. Future work will include selecting one of the patterns for immobilization of glucose oxidase allowing us to realize a fully functional glucose sensor. [ABSTRACT FROM AUTHOR]

This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO2 and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions. [ABSTRACT FROM AUTHOR]

This paper presents in-memory computing using fast write/erase quantum dot (QD) nonvolatile random access memory (NVRAM). In comparison to NVMs, multi-state NVRAMs offer enhanced Compute-In-Memory capability for applications in deep neural network architecture. Dot product is the methodology that enables an array structure for multiply and accumulate (MAC) operation. We show an approach to dot product computation using multi-state quantum dot channel (QDC) FETs and QD-NVRAM. [ABSTRACT FROM AUTHOR]