Search

High temperature or temperature nonuniformity has become a serious threat to performance and reliability of high-performance integrated circuits (ICs). Since the temperature in a 3-D IC is mainly determined by a power distribution across tiers, this article proposes a novel method to allocate modules to tiers while exploring a better power distribution according to the hyperparameter optimization technique. In addition, we integrate the sub-3-D thermal mask into the analytical formulation to interleave high power consumption modules in contiguous tiers during distributing modules over placement regions so that it is possible to insert through-silicon vias (TSVs) around high power modules to further reduce the temperature at a later stage. Since the temperature in a tier will be changed every time the locations of TSVs in its lower tier are moved, we also propose a procedure to update the temperature map before refining locations of TSVs. Experimental results have demonstrated that the proposed methodology can effectively reduce the temperature of a 3-D IC with a slight increase in the wirelength. Moreover, its runtime is quite fast.

This article proposes a novel approach to handle macro placement. Previous works usually apply the simulated annealing (SA) algorithm to handle this problem. However, the SA-based approaches usually have difficulty in handling preplaced macros and require longer runtime. To resolve these problems, we propose a macro placement procedure based on the corner stitching data structure and then apply an efficient and effective simulated evolution algorithm to further refine placement results. In order to relieve local routing congestion, we propose to expand areas of movable macros according to the design hierarchy before applying the macro placement algorithm. Finally, we extend our macro placement methodology to consider dataflow constraint so that dataflow-related macros can be placed at close locations. The experimental results show that our approach obtains a better solution than a previous macro placement algorithm and a tool. Besides, placement quality can be further improved when the dataflow constraint is considered.

High temperature or temperature nonuniformity has become a serious threat to performance and reliability of high-performance integrated circuits (ICs), which makes the thermal effect turn into a nonignorable issue in the circuit design or the physical design. In order to estimate temperature accurately, the locations of modules have to be determined in advance, which makes an efficient and effective thermal-aware floorplanning play a more important role. Hence, this article proposes a differentiable nonlinear placement model that can optimize temperature and minimize wirelength at the same time without needing to construct a congestion map. In addition, to avoid inducing longer wirelength while optimizing temperature, we propose some techniques, such as thermal-aware clustering, shrink of hot modules, or thermal-force modulation in the multilevel framework. The experimental results demonstrate that temperature and wirelength are greatly improved by our method compared to Corblivar. More importantly, our runtime is quite fast and the fixed-outline constraint can also be satisfied.

This paper introduces a routability-driven macro placement algorithm for mixed-size circuits and pays special attention to the effect of regular placement of macros. Once macros are placed with regularity, powerplanning will become easier and better routability can be obtained. Our methodology consists of two stages. First, placement prototyping stage distributes cells and macros over a placement region while keeping those macros and cells with a strong connection and in similar hierarchies tied together. This is facilitated by clustering macros and cells properly in advance. In the second stage, a deterministic macro legalization algorithm is proposed to arrange macros without deteriorating the result obtained in the previous stage. Although several macro legalization algorithms have been proposed in recent years, most of these works adopt the simulated annealing algorithm which usually takes longer runtime. Moreover, they either cannot handle preplaced macros or require preplaced macros to be abutted to chip boundaries. Unlike these approaches, our method iteratively places a macro by extracting available space for it. Experimental results demonstrate the efficiency and effectiveness of our method according to real industry circuits.

As the power consumption of an electronic equipment varies more severely, the device voltages in a modern design may fluctuate violently as well. Consideration of dynamic IR-drop becomes indispensable to current power network design. Since solving voltage violations according to all power consumption files in all time slots is impractical in reality, this paper applies a clustering based approach to find representative power consumption files and shows that most IR-drop violations can be repaired if we repair the power network according to these files. In order to further reduce runtime, we also propose an efficient and effective power network optimization approach. Compared to the intuitive approach which repairs a power network file by file, our approach alternates between different power consumption files and always repairs the file which has the worst IR-drop violation region that involves more power consumption files in each iteration. Since many violations can be resolved at the same time, this method is much faster than the iterative approach. The experimental results show that the proposed algorithm can not only eliminate voltage violations efficiently but also construct a power network with less routing resource.

Although 3-D floorplanning has been studied widely, routability which is a very important issue in modern integrated circuit (IC) designs is rarely discussed. Floorplanning in 3-D ICs is much difficult than that in 2-D ICs because of large difference in sizes between modules and through silicon vias (TSVs), which are key components in 3-D ICs. And the locations of TSVs have great impact on wirelength and routability in resulting floorplans. Hence, this paper proposes a TSV-aware 3-D floorplanning methodology which can consider wirelength and routability at the same time under the fixed-outline constraint. Unlike most of previous works which completely apply the simulated annealing algorithm, our methodology mainly apply deterministic algorithms to resolve the problem. Thus, our approach is more efficient and flexible than previous works. Experimental results have demonstrated that the proposed methodology can significantly reduce routing congestion in 3-D ICs with a slight increase in wirelength.

As technology advances, power consumption becomes a big challenge in modern very large-scale integration designs. To resolve this problem, power-gated technology has been widely adopted in circuit designs. Since the turn-on sequence of power switches has a great impact on the rush current, wake-up, and sequence times of a power gating design, this paper proposes a methodology to construct a hybrid routing structure to connect power switches. Our hybrid routing structure can induce less rush current and satisfy timing constraints because a better daisy chain is constructed. To find members of the daisy chain, an integer linear programming algorithm is used to pick up suitable power switches. To determine suitable depth of a daisy chain, we propose a model for a power gating design and induct precise equations to estimate voltage and rush current equations according to the model. All of our experiments are based on industrial designs and measured by vendor tools. The experimental results demonstrate the efficiency and effectiveness of our design methodology.

Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent power efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also hard to quickly evaluate the feasibility of a given specification in a process node. This paper presents a systematic sizing procedure for asynchronous SAR ADCs based on design considerations. A sizing tool based on the proposed design procedure is also implemented, the sizing results of which are highly competitive in comparison with other state-of-the-art manual works. Moreover, the sizing time is relatively short due to the efficient and effective search algorithms employed. In addition to the simulation results, two silicon proofs with different specifications and process nodes are provided to demonstrate the feasibility of this design methodology.

Reliability of a P/G network is one of the most important concerns in a chip design, which makes powerplanning the most critical step in the physical design. Traditional P/G network design mainly focuses on reducing usage of routing resource to satisfy voltage drop and electromigration constraints according to a regular mesh. As the number of macros in a modern design increases, this style may waste more routing resource and make routing congestion more severe in local regions. In order to save routing resource and increase routability, this paper proposes a delicate powerplanning method. First, we propose a row-style power mesh to facilitate connection of pre-placed macros and increase routability of signal nets in the later stage. Besides, an effective power stripe width which can reduce wastage of routing resource and provide stronger supply voltage is found. Moreover, we propose the first work to use the linear programming algorithm to minimize P/G routing area and consider routability at the same time. The experimental results show that routability of a design with many macros can be significantly improved by our row-style power networks.

This paper proposes a general floorplanning methodology which can be applied to 3D ICs with an arbitrary bonding style. Some researches have shown that a 3D IC with the hybrid bonding style, which includes face-to-back and face-to-face, may obtain better results than that simply using the face-to-back bonding style. We respectively present an approach to assign modules to tiers for each kind of bonding style. Further, a new utilization function, called cosine-shaped function, is proposed to estimate utilizations of bins required by the analytical-based approach. Our experimental results show the cosine-shaped function can obtain a little better result than the bell-shaped function on IBM benchmarks for 2D floorplanning. We also show that the proposed 3D floorplanning methodology consumes less TSVs and induces shorter wirelength compared to previous work in the hybrid bonding style.

As advances in manufacture technology, leakage current increases dramatically in modern ICs. By turning off supply voltage in a low-power domain with power switches, power gating becomes a useful technique in resolving this problem. Since number and locations of power switches have great impact on chip area and IR-drop, an efficient and effective approach to insert power switches is required for the power gating designs. Unlike previous works using the greedy algorithm to handle this problem, this paper uses a simplified model to approximate required equivalent resistance of power switches in a low-power domain, and then determines number and types of power switches based on the value. In order to reduce impact on preplaced standard cells, we also propose a mathematical approach to find locations with less placement density to place power switches. The proposed methodology was integrated into a real-design flow. Experimental results demonstrate that our approach can insert less number of power switches and still satisfy the IR-drop constraint than other approaches.

The paper introduces a routability-driven placement prototyping algorithm for hierarchical mixed-size circuits and pays special attention to regular placement of macros. The three-stage algorithm has become the most popular placement approach for commercial design flows, where placement prototyping plays a critical role in the algorithm because distribution of cells and macros is mainly determined by it. SOC circuits usually contain sets of macros which have identical shapes and are in similar hierarchies. If these macros can be placed regularity, powerplanning will become easier and better routability may be obtained. To consider placement regularity, the paper proposes a physical aware clustering algorithm which is possible to cluster two objects with large area. Experimental results have demonstrated effectiveness of our methodology according to industrial benchmarks tested by a real design low.

This paper presents a two-stage approach to handle fixed-outline floorplanning for mixed size modules, named F-FM. F-FM combines the advantages of the analytical approach and the slicing tree representation. Thus, it is not only suitable for handling fixed-outline floorplanning but also can be extended to handle other important issues in floorplanning such as routability or thermal effect in addition to wirelength. Recently, low power has become big challenges in very large-scale integration designs, which makes voltage-island driven floorplanning more important than ever. Although the problem has been discussed by previous works, no paper considers signal wirelength, powerplanning, and voltage drop at the same time under the fixed-outline constraint. Thus, this paper extends F-FM to handle this problem and consider these issues by properly dividing modules in a voltage domain into several islands. The experimental results show our approach obtains the best results in these problems.