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A method of accurately estimating the I/sub 0/ (critical current) of a Josephson junction (JJ) with thermal noise was developed by measuring the effective thermal noise temperature of a JJ. The effective thermal noise temperature of various JJ devices was measured and calculated. The JJ devices evaluated included inductively and resistively coupled logic devices and JJ devices in the presence of various noise sources. The noise sources included room-temperature resistors, switched JJ devices, and JJ devices in the linear I-V region beyond the gap. The R/sub NN/ compensator is shown to result in a noise temperature of about 6 K at an interferometer. The addition of a shunt junction lessens the noise penalty introduced by the compensator. A switched isolation interferometer in a two-input AND gate contributes negligible noise at the injection device. It is also shown that bandwidth connections to room-temperature equipment result in very large excess noise and require special input and output circuits on the chip. >

GaAs metal‐semiconductor field‐effect transistors (MESFETs) and other integrated‐circuit elements were characterized by including extensive process test sites on wafers with digital logic and memory circuits. A self‐aligned, refractory‐gate enhancement/depletion (E/D) process was employed which included 47SiF+ channel and source/drain implants, capless arsenic overpressure furnace annealing, WSi0.11 gate metal with in situ sputter cleaning, Ni‐Au‐Ge ohmic contacts, Si3N4 or SiO2 insulation, and Ni‐Au wiring. On‐water threshold voltage standard deviations as low as 31 mV for 1‐μm E‐FETs and 49 mV for 1‐μm D‐FETs were measured using 51‐mm standard semi‐insulating liquid‐encapsulated Czochralski GaAs substrates. Threshold voltage control from wafer to wafer was of order 100 mV. Schottky diode barrier height was about 0.73 eV with an ideality of 1.2, although small self‐aligned Schottky gates often showed excess conduction believed to occur at the gate edges. FET square‐law coefficient, subthreshold leakage, ...

A GaAs MESFET 16x16 crosspoint switch has been fabricated on a 3-mm x 4-mm chip using a 1-μm super buffer logic (SBL) design containing approximately 10000 FETs and operating at 800 mW of power. A 99% confidence bit error rate (BER) better than 1*10/sup -3/ was obtained at 1.7 Gb/s rate using a 2/sup 7/ -1 pseudorandom NRZ (nonreturn-to-zero) sequence. The BER test was done on one path using a probe card. The chip has 255 out of 256 good crosspoints. The bad crosspoint was a repeating error from a mask defect. An advanced refractory-gate MESFET process was used to fabricate the chip. A lightly doped drain structure was used to reduce parasitic gate capacitance while maintaining acceptable source resistance, to reduce short-channel effects, to increase breakdown voltage compared to devices where the heavy source/drain implant is directly self-aligned to the gate edge. >