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A prototype of a high-bandwidth parallel event builder has been designed and tested. The architecture is based on a simple switching network and is adaptable to a wide variety of data acquisition systems. An eight-channel system with a peak throughput of 160 Mbytes/s has been implemented. It is modularly expandable to 64 channels (over 1 Gbyte/s). The prototype uses a number of relatively recent commercial technologies, including very-high-speed fiber-optic data links, high integration crossbar switches, and embedded RISC processors. It is based on an open architecture which permits the installation of new technologies with little redesign effort. >

A system to collect and process data at high rate, 53 MHz, from a silicon microstrip detector has been developed. The system is implemented using the FASTBUS standard and modularized at the board level in 128 channel increments. The system includes the following features: zero dead time readout for average trigger rate as high as 1 MHz; pipelined triggers and event readout; programmable data delay of up to 4.8 mu s; FASTBUS system readout; histogram readout option; and multiple high-speed bipolar process ASICs (application-specific integrated circuits). A general block diagram of data flow for the SSD (silicon strip detector) readout is provided. All the modules used for the SSD readout were tested individually to satisfy single board test requirements. Attention is given to SSD hardware for E771, a fixed target experiment designed to study the production of B hadrons by an 800 GeV/c proton beam. >

A synchronous silicon strip readout system capable of zero dead-time readout at average trigger rates in excess of 1 MHz is described. The system is implemented in Fastbus, uses pipelining techniques, and includes point-to-point fiberoptic data links to transmit detector digital data. Semicustom ASIC (application-specific integrated circuit) chips are used to amplify, discriminate, and logically combine track data before encoding. The overall system, each major Fastbus module, and the functional aspects of the ASIC chips are described. >

The FASTBUS Segment Interconnect (SI) provides a communication path between two otherwise independent, asynchronous bus segments. In particular, the Segment Interconnect links a backplane crate segment to a cable segment. All standard FASTBUS address and data transactions can be passed through the SI or any number of SIs and segments in a path. Thus systems of arbitrary connection complexity can be formed, allowing simultaneous independent processing, yet still permitting devices associated with one segment to be accessed from others. The model S1 Segment Interconnect and the Cable Segment Ancillary Logic covered in this report comply with all the mandatory features stated in the FASTBUS specification document DOE/ER-0189. A block diagram of the SI is shown.

Hadron rejection against electron signal of a combined system of electromagnetic and hadron calorimeter has been studied. Data was taken at M4 beam line of Fermilab at energies from 25 GeV to 150 GeV. Hadron rejection of electromagnetic calorimeter is greatly improved by the use of hadron calorimeter information. The details of the results are discussed.

A prototype module for the electromagnetic shower calorimeter has been constructed and its characteristics have been measured. It consists of 38 layers of planar proportional chambers interleaved with 3 mm thick lead plates. The proportional chamber is made of conductive plastic tubes as a dc cathode and pickup electrodes as an rf cathode. The pickup electrodes are copper-clad G-10 panels etched with finely segmented patterns which, when assembled, form complete conical towers. The module was tested using high energy electron and hadron beams of energy range from 25 GeV to 150 GeV. Energy resolution is 24% E( GeV ) , and the position resolution is 1.5 mm or better at and above 50 GeV. The lateral and longitudinal distributions of the energy deposit are studied and they are applied to π e discrimination.

Bi-dimensional drift chambers up to 2 m × 1.5 m size using flexible printed circuit balanced delay lines are built. The delay line has good transmission characteristics with 85 Ω impedance and good longitudinal coordinate resolution with geometrical and constructional advantages.

The FASTBUS prototyping system provides a fast, simple, way to get started with FASTBUS and for the development of FASTBUS modules. The use of CAE (computer-aided engineering) tools, combined with standard parts and simulation capability, allows the designer to produce a working design quickly and reduce the hardware debugging time. By starting with a previously designed, general-purpose FASTBUS module, the designer can quickly apply the FASTBUS interface of a design and concentrate on his application. A simulation capability allows the beginning FASTBUS designer to become familiar with FASTBUS operations and timing rapidly. The CAD (computer-aided design) tools are then used to produce a PC (personal computer) board, the interface portion of which is already done and needs only the addition of the users application. The same test software produced in the simulation may be used to test the finished module. The author describes the system and reviews its current status. >

All CDF event data are collected in a multilevel FASTBUS network. At the lowest level of this network, MEP/MX and SSP scanners read and buffer data from RABBIT and FASTBUS front end systems. Operation of these front end scanners is coordinated by the Trigger Supervisor module which initiates parallel readout after receiving Level 1 and Level 2 triggers. Dataflow from scanners to consumer processes on host VAX computers is supervised by the Buffer Manager which directs an Event Builder to collect and format data from a set of scanner modules. This system is designed to allow partitioning into semi-independent sections for parallel development and calibration studies.