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We have been investigating the levitation system without any mechanical contact which is composed of a field-cooled ring-shaped high temperature superconducting (HTS) bulks [1] . In this proposed levitation system, the trapped magnetic field distributions of stacked HTS bulk are very important. In this paper, the spherical solenoid magnet composed of seven solenoid coils with different inner and outer diameters was designed and fabricated as a new magnetic source. The fabricated spherical solenoid magnet can easily make a homogeneous and various magnetic field distributions in inner space of stacked HTS bulk annuli by controlling the emerging currents of each coil. By using this spherical solenoid magnet, we tried to make a large magnetic field gradient in inner space of HTS bulk annuli, and it is very important on the levitation of magnetic substances. In order to improve the levitation properties of magnetic substances with various sizes, the external fields were reapplied to the initially trapped HTS bulk magnets. We could generate a large magnetic field gradient along the axial direction in inner space of HTS bulk annuli, and obtain the improved levitation height of samples by the proposed reapplied field method.

We achieved stable levitation of cylindrical permanent magnets and irons using stacked ring-shaped high temperature superconducting (HTS) bulks with 20 mm ID, 60 mm OD and 50 mm height, and those were magnetized by field cooling method. The levitation characteristics of permanent magnets and iron samples located in the inner space of that levitation system were investigated experimentally. Iron samples with needle-shape and smaller than 1 mm diameter could not levitate stably. However, we found that the high strength of magnetized field was not necessary to levitate small needle-shaped irons. In order to levitate them, we need a uniform magnetic field in radial direction, so, a spherical solenoid magnet that can easily make a homogeneous magnetic field in inner space of HTS bulk annuli was developed. The spherical solenoid magnet, composed of seven solenoid coils with different inner and outer diameters, was designed by an electromagnetic analysis and fabricated.

High-frequency characteristics of SOI lateral BJTs designed for 2-GHz radio frequency (RF) applications are measured and compared for various link-base length, emitter width, and collector structure. Based on experimental data and device simulation, degradation mechanism of cutoff frequency for shorter link-base is analyzed. By suppressing external base-induced effects, peak cutoff frequency is increased from 10 GHz to 15 GHz.

Summary An unusual case of verrucous carcinoma of the face with a massive infiltration of neutrophils was found in a 60-year-old Japanese man who presented with a scaly, crusty tumour studded with pustules of 3 years duration on the left check. Historical examination showed a proliferation of deceptively benign-looking epidermal cells with an intact basement membrane, accompanied by a dermal infiltration of neutrophils and mononuclear cells and formation of microabscesses containing multinucleate giant cells, suggesting deep fungal infection or blastomycosis-like pyoderma. The lesion, however, was unresponsive to antifungal or antibacterial treatments and ultimately attained a considerable size in the following months. Based on the findings of repeat biopsy conducted 4 months later indicating further deeper invasion, a diagnosis of verrucous carcinoma of the face was made, and a total excision of the tumour and left cervical lymph node dissection were finally carried out. It can be speculated that aberrant production of leucocyte chemotactic cytokines such as interlcukin-8 by dysplastic keratinocytes, subsequent neutrophil infiltration/serum permeation, generation of leucotactic anaphylatoxin C5a from serum through complement activation and of lipid chemotactic factors (leukotriene B4 and 12-hydroxy-cicosatetraenoic acid) by infiltrating leucocytes and/or dysplastic keratinocytes provoked the characteristic accumulation of neutrophils in the verrucous carcinoma of this case.

A 512K×8b EPROM fabricated in 0.8μm, CMOS with a cell size of 9μm2and a chip size of 5.9×14.9mm2will be reported. The device programs at a rate of 10μs per byte, reads with an access time of 120ns and draws 10mA of active current.

A novel device structure to realize high-performance SOI lateral BJTs is presented. A metal-backed single-silicon external base electrode and a simple SOI structure achieve low base resistance and low parasitic capacitances, respectively. Due to the minimal parasitics, the device exhibited an fmax of 62 GHz with a low power dissipation per emitter area of 0.55 mW//spl mu/m/sup 2/.

Three samples with different thicknesses of polysilicon-silicon interfacial oxide were prepared. The influence of the interfacial oxide on the electrical characteristics of 0.8- mu m BiCMOS VLSIs was studied. From the results, the maximum interfacial oxide thickness allowed for BiCMOS LSIs was determined. To control the interfacial oxide thickness, the ball-up mechanism was studied using HRXTEM combined with energy-dispersive X-ray spectroscopy measurements. The optimum heat treatment after emitter deposition to realize 0.5- mu m BiCMOS VLSI was also determined. >

A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized. >

Application-specific integrated circuits (ASICs) with high-performance embedded memory array with suitable design route have considerable merits in terms of system speed, scalability with technology and system cost. The choice of design approach according to applications is critical. For highly memory-rich applications, one of the recently developed memory ASICs, an integrated cache memory is described. Another example suited for large-size random logic and high-density memory is a structure array approach. A recently developed 72 K track-free gate array with 1 Mb DRAM is described. >

A new Constant Current Voltage-Down Converter and a new Partially Inverted data BUS Architecture are proposed. The proposed VDC reduces Vdd1/Vss1 noise to less than 20%, and the proposed BUS architecture reduces Vdd1/Vss1 noise to about 1/n using only n-1 bit flag signals.

Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.

A dual layer BL array and a Vcc/Vss hybrid precharge sensing scheme has been proposed. The array affords the maximum memory cell density and relaxed sense amplifier layout which is as wide as the conventional folded BL sense amplifier layout. The Vcc/Vss hybrid precharge scheme gives the doubled operation voltage for sensing compared with the conventional half Vcc precharge method without the BL charge/discharge current increase.

Presents two novel sophisticated experimental procedures for precise estimation of Si interstitial and vacancy diffusion coefficients, supported with a result from a three-dimensional process simulation system. One is impurity profile monitoring under well-controlled injected flux of point defects in three dimensional space, while the other one is in-situ TEM (transmission electron microscope) observation of the regrowth region damaged with Si ion-implantation. The authors also present a proposal for nonequilibrium Si self-diffusion process modeling based on these results. Application of the model to the ULSI process design phase is discussed. >

A novel device structure and simple process technology for realizing low-power/high-performance SOI lateral BJTs are presented. Low base resistance has been achieved by employing a self-aligned external base formation process. Due to reduced parasitics, the fabricated device exhibited an f/sub max/ of 31 GHz, the highest value for an SOI BJT reported so far.

Multiple factors affect skin pigmentation, including those that regulate melanocyte and/or keratinocyte function. Such factors, particularly those that operate at the level of the melanosome, are relatively well characterized in mice, but the expression and function of structural and enzymatic proteins in melanocytes in human skin are not as well known. Some years ago, we generated peptide-specific antibodies to murine melanosomal proteins that proved to be instrumental in elucidating melanocyte development and differentiation in mice, but cross-reactivity of those antibodies with the corresponding human proteins often was weak or absent. In an effort to characterize the roles of melanosomal proteins in human skin pigmentation, and to understand the underlying mechanism(s) of abnormal skin pigmentation, we have now generated polyclonal antibodies against the human melanocyte-specific markers, tyrosinase, tyrosinase-related protein (TYRP1), Dopachrome tautomerase (DCT) and Pmel17 (SILV, also known as GP100). We used these antibodies to determine the distribution and function of melanosomal proteins in normal human skin (adult and newborn) and in various cutaneous pigmented lesions, such as intradermal nevi, lentigo simplex, solar lentigines and malignant melanomas. We also examined cytokeratin expression in these same samples to assess keratinocyte distribution and function. Immunohistochemical staining reveals distinct patterns of melanocyte distribution and function in normal skin and in various types of cutaneous pigmented lesions. Those differences in the expression patterns of melanocyte markers provide important clues to the roles of melanocytes in normal and in disrupted skin pigmentation.

Macrophage migration inhibitory factor (MIF) was originally identified several decades ago as a lymphokine-derived protein that inhibited monocyte migration. Recently, it has been reported that MIF has D-dopachrome tautomerase, phenylpyruvate tautomerase and thiol protein oxidoreductase activities, although the physiological significance of those activities is not yet clear. Here we show that MIF is able to catalyze the conversion of dopaminechrome and norepinephrinechrome, toxic quinone products of the neurotransmitters dopamine and norepinephrine, respectively, to indole derivatives that may serve as precursors to neuromelanin. Since MIF is highly expressed in human brain, these observations raise the possibility that MIF participates in a detoxification pathway for catecholamine products and could therefore have an important role for neural tissues. The potential role of MIF in the formation of neuromelanin from catecholamines is also an extremely interesting possibility.

Stable levitation of cylindrical iron and permanent magnet (PM) samples of various sizes has been achieved by using high temperature superconducting (HTS) bulk annuli which were magnetized by field cooling (FC) method. In this paper, we examined the forces acting on iron and PM samples levitating in the inner space of HTS bulk annuli. The levitation forces of the 3 stacked HTS bulk system (3 bulks system) have been compared with the 2 stacked HTS bulk system (2 bulks system) having a gap between the bulks. In our experiments, the levitation force increases with increasing the magnetization field strength, the strength of magnetic flux density of PM, and the sample size. The levitation force of the 2 bulks system was better than the 3 bulks system, and we found that the levitation force using the field in magnetized HTS bulk systems strongly depends on the strength of the magnetic flux density of the sample and the magnetic field gradient in the levitating space.

Hypocitraturia is defined as one of the risk factors for calcium oxalate (CaOx) nephrolithiasis because citrate inhibits CaOx crystallization and retards its crystal growth. However, the clinical importance of hypocitraturia is not yet clearly understood.

Summary Acral pseudolymphomatous angiokeratoma of children (APACHE) is a new clinical entity that is characterized by angiomatous papules on the extremities. We report a case APACHK in a 14-year-old Japanese girl with asymptomatic red and violaceous papules and nodules on the ring finger of the left hand. Histological and immunohistochemical studies of our patient indicated that APACHE is a pseudolymphoma rather than an angiokeratoma.

We report a case of Ki-1 lymphoma that developed in a 16-year-old youth who had suffered from multicentric reticulohistiocytosis for 10 years. Over the past 3 years he had had a peculiar sclerosing lesion of the leg for which oral prednisone 5 mg daily was tried for one year, with a moderate effect. He developed a marked swelling of the inguinal lymphadenopathy on the same side as the affected leg lesion, which also developed a prominent swelling of the skin surrounding the sclerosed area. Immunohistochemical analysis of the lymph node biopsy revealed the features of Ki-1 lymphoma. This is the first case of association of multicentric reticulohistiocytosis with Ki-1 lymphoma.

A 1- mu A-retention, 4-Mb SRAM with a thin-film-transistor (TFT) load cell, fabricated in a 0.5- mu m triple-poly-Si (first- and third-level W-polycide) double-Al CMOS technology is described. A 200-fA/b retention current is achieved. utilizing the PMOS-type TFT, in which the n/sup +/ diffusion area of the driver transistor acts as a gate electrode of the TFT. The RAM, which has a built-in voltage down converter (VDC), operates with a 3.3-V supply from a standard 5 V+or-10% external supply. In the battery backup mode, an on-chip external-supply-level sensor disables the VDC, and the retention current of the RAM is reduced to 1 mu A. >

A Monte Carlo simulator has been developed that can trace random nucleation and regrowth characteristics for silicon-on-insulator MOS transistors and can predict the distribution of device characteristics. Activation energies for nucleation and regrowth in solid-phase were derived to be 3.9 eV and 2.8 eV, respectively. Localized states caused by the regrowth boundary were observed as a function of regrown grain size where values were two orders of magnitude larger than for bulk MOS. Threshold voltage shift and carrier mobility could be interpreted mainly in terms of the density-of-states and boundary structure; the distribution of threshold voltage and mobility were predicted closely by the Monte Carlo simulator

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.

Silicon VLSI, as a host of devide physics and novel process/device technology as well as various engineering challenges has shown remarkable progress in recent years. Realization of smaller dimension, higher integration density and less power dissipation have been a guiding principle for VLSI technology, and have resulted in significant achievements both in basic understanding and practical VLSI devices mostly in digital electronics. This paper reviews the current state of the art in device/process technology and modeling, placing emphasis on MOS VLSI's, where issues accompanied with scaling down of MOS transistors, miniaturization of passive region such as isolation region and interconnection wiring region are discussed. Also, discussed will be modeling for process, device and combined effort for integrated simulation of both process and device.

A high-density (512K-word/spl times/8-b) erasable programmable read-only memory (EPROM) has been designed and fabricated by using 0.8-/spl mu/m n-well CMOS technology. A novel chip layout and a sense-amplifier circuit produce a 120-ns access time and a 4-mA operational supply current. The interpoly dielectric, composed of a triple-layer structure, realizes a 10-/spl mu/s/byte fast programming time, in spite of scaling the programming voltage V/SUB PP/ from 12.5 V for a 1-Mb EPROM to 10.5 V for this 4-Mb EPROM. To meet the increasing demand for a one-time programmable (OTP) ROM, a circuit is implemented to monitor the access time after the assembly. A novel redundancy scheme is incorporated to reduce additional tests after the laser fuse programming. Cell size and chip size are 3.1/spl times/2.9 /spl mu/m/SUP 2/ and 5.86/spl times/14.92 mm/SUP 2/, respectively.

A submicrometer-rule interconnection structure of the Al-Si layer to the BF 2 +-implanted Si region is described. The contact resistance of Al-Si to BF 2 +-implanted Si increases more than those to B+- or As+-implanted Si, as contact hole size is scaled down to around 1 µ2. Through SEM and TEM analyses, it is found that solid phase epitaxial growth of Si takes place on the contact interfaces, where crystalline defects induced by BF 2 +implantation act as seeds. Thus, the effective metal contact area to Si is reduced very much. In order to realize a stable metallization system, a TiN/Ti barrier metal structure is introduced. The TiN/Ti structure is optimized in terms of contact resistance and contact barriers, and its feasibility for submicrometer-rule CMOS VLSI's is clarified.

The system, circuit, layout and device levels of an integrated cache memory (ICM), which includes 32 kbyte DATA memory with typical address to HIT delay of 18 ns and address to DATA delay of 23 ns, are described. The ICM offers the largest memory size and the fastest speed ever reported in a cache memory. The device integrates a 32 kbyte DATA INSTRUCTION memory, a 34 kbit TAG memory, an 8 kbit VALID flat, a 2 kbit least recently used (LRU) flag, comparators, and CPU interface logic circuits on a chip. The inclusion of the DATA memory is crucial in improving system cycle time. The device uses several novel circuit design technologies, including a double-word-line scheme, low-noise flush clear, a low-power comparator, noise immunity, and directly testable memory design. Its newly proposed way-slice architecture increases both flexibility and expandability. >

A new EPROM named SEPROM, based on a modified SEPOX process, is proposed and evaluated. The SEPROM offers a process compatibility to logic LSI's with higher packing density, since the area of the second gate oxide is equal to that of the first gate oxide. To improve the coupling capacitance ratio, which relates to write and read operations, a thin second gate oxide is required for the SEPROM cell at a risk of degradation in charge retention characteristics. A measured test device, however, shows sufficiently good characteristics both in programming and charge retention, due to the desirable structure of the cell. The SEPROM structure appears to be practical and promising for both EPROM and logic device applications.

Field isolation technology is described for small geometry VLSI's in which selective polysilicon oxidation is essential. The technology, also known as SEPOX, offers resist pattern reproducibility in field oxide, while maintaining crystal perfection in the substrate. By a series of experiments, high oxide reliability resulting from a white ribbon-free nature, long lifetime from C-T measurement, and small leakage currents in a reverse biased p-n junction were obtained, as well as a small geometry structure. The feasibility of this technology for MOS LSI's were examined in a 3-/spl mu/m rule memory chip, and a reasonable yield and reliability were obtained. The physical limitations of SEPOX were also considered and submicrometer capability was confirmed.

A 1-Mb (128K*8) pseudostatic RAM (PSRAM) is described. A novel feature of the RAM is the inclusion of a virtually static RAM (VSRAM) mode, while being fully compatible with a standard PSRAM. The RAM changes into the VSRAM mode when the RFSH pin is grounded, even in active cycles. The RAM can be used either as a fast PSRAM of 36-ns access time or as a convenient VSRAM of 66-ns access time. The typical operation current and data-retention current are 30 mA at 160-ns cycle time and 30 mu A, respectively. In order to achieve high-speed operation, low data-retention current, and high reliability, the RAM uses delay-time tunable design, a current-mirror timer, hot-carrier resistant circuits, and an optimized arbiter. These technologies are applicable to general advanced VLSIs. >

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz. >

When a drug is instilled into the bladder provided with experimental cystitis, the drug could be transferred into the serum. We studied the transfer of mecillinam into the serum, and found that the extent of transfer varied with the method to cause experimental cystitis and also occurred even in the normal bladder. It was suspected that in the inflamed bladder, a part of mecillinam excreted into the urine would possibly be transferred again into the serum through bladder wall.

Two step impact ionization phenomena near the high electric field drain region are characterized, both theoretically and experimentally, in small geometry NMOS and PMOS structures. Influences of primary and secondary impact ionized carrier flows are quantitatively considered as design constraints in high density MOS memories, more specifically for CMOS devices and also for poly-Si resistor load RAM cells.

A lum-rule interconnection structure is described especially in terms of contact characteristics of Al-Si to BF 2 +-implanted Si.(1-5) It is found that contact resistance of Al-Si to BF 2 +-implanted Si increases more drastically than those to B+- and As+-implanted Si, as contact hole size is reduced down to around lum2. With SEM and TEM analyses, a model that Si solid phase epitaxial growth take place on contact surface, where crystalline defect induced by BF 2 +implantation act as the seed, and thus effective metal contact area to Si is drastically reduced, is established. As a solution for this problem, a new metallization system with a TiN barrier metal is proposed and its feasibility is confirmed.

The architectural aspects of a newly deveoped integrated cache memory is described in this paper, which includes 32Kbyte DATA memory with a typical ADDRESS to HIT delay, the largest memory size and fastest speed ever reported as an integrated cache memory[1]. The device integrates data/instruction memory, tag memory and a comparator on a chip. It serves as a cache memory of several host MPUs by aluminum masterslice.

The trade off between circuit performance and reliability of CMOS devices is theoretically and experimentally examined in detail down to sub micrometer gate length including various effects such as mobility degradation, reliability physics, parasitic capacitances and parasitic resistances. Based upon these cosideration, a new scaling scenario has been proposed to determine power supply voltage for half and lower sub micrometer CMOS devices. The new scaling scheme has been applied to O.6um CMOS device and it has been verified that the power supply voltage can be scaled down maintaining high circuit performance with high reliability.

This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region. In that context, the authors review bulk CMOS technology from 2µm to sub-micron features based upon existing device characteristics, and also discuss directions for further downward scaling.

A shallow P-type buried layer has been applied to the poly Si load static memory cell in order to suppress α-particle induced soft errors. The effects of the P-type buried layer for suppression of carrier collection due to the funnelling field is verified by a transient 2-carrier 2-dimentional simulator. Various profiles for the buried layer have been tested for CMOS static RAM performances. By means of the optimized process, soft error rate is reduced by three orders of magnitude compared with that of the unprotected structure, and no performance degradation has been observed.