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Printed circuit board (PCB) design can be supported to a high degree by adding AI modules to the design system. Predictions from these modules can be made available to the designer in order to speed up circuit design and make it more efficient. Problems regarding signal integrity (SI) can be detected in time by providing hints on component connection or routing. However, the optimization and ML methods used in this context are usually very sophisticated (e.g., Bayesian optimization). Therefore, the design parameters provided by the AI modules must be accepted without further insights (for the experienced as well as the inexperienced designer). In this paper, a decision tree for anomaly detection and SI verification is presented, which by nature of this algorithm provides insights to the decisions made to obtain the proposed design parameters. Using a point-to-point (P2P) network as an example, the prediction accuracy of the AI model is investigated. It is shown that assessing SI effects with a decision tree provides a simple approach to obtain the suggested design. Furthermore, the predictions of the decision tree can be verified against the design rules.

The effects of parameters affecting the input impedance of a power delivery network (PDN) are investigated. It is considered that the size of the power plane and the number of associated planes in the PCB layout, apart from the decoupling capacitor, have an effect on the impedance behavior within a certain frequency range. An artificial neural network (ANN) is trained using the generated data utilizing a process to generate suitable input for training a machine learning (ML) module, which is able to predict the impedance profile of the PDN. In order to obtain a more accurate prediction, Bayesian optimization is implemented and the results are compared to commercial power integrity (PI) software.

Signal integrity (SI) is an essential part in assuring the functionality of microelectronic components on a printed circuit board (PCB). Depending on the complexity of the designed interconnect structure, even the experienced PCB developer might be reliant on multiple design cycles to optimally configure the PCB parameters, which eventually results in a very complex, time-consuming and costly process. Under these aggravating conditions, artificial intelligence (AI) models may have the potential to support and simplify the SI-aware PCB design process by building predictive models and proposing design solutions to streamline the existing workflows and unburden the PCB designer. In this paper, the AI approach is divided into two separate stages consisting of neural network (NN) regression in the first step and parameterization of the PCB net structure in the second step. First, the NN models are applied to learn the relationship between the electrical parameters and the resulting signal quality captured by domain-oriented signal features in the time domain. Second, based on the trained NN models, on the one hand, the k-nearest neighbor (kNN) method is utilized to select solution candidates within the feature space, while on the other hand, genetic algorithms (GA) are applied to directly optimize the parameters of the interconnect structure. Moreover, the influence of the simulation abstraction level is investigated by comparing simulation data originating from linear and I/O buffer information specification (IBIS)-based non-linear modeling of the integrated circuit (IC) characteristics concerning the prediction accuracy and direct transferability. Finally, transfer learning concepts are evaluated to exchange learned knowledge representations between the different modeling of the IC characteristics to improve data efficiency and reduce computational complexity.

Currently, the electrification of the drive train of passenger cars takes place, and the task of obtaining precise knowledge about the condition of the on board batteries gains importance. Due to a flat open circuit voltage (OCV) to state of charge (SoC) characteristic of lithium ion batteries, methods employed in applications with other cell chemistries cannot be adapted. Exploiting the higher significance of the impedance for state estimation for that chemistry, new impedance based features are proposed by this work. To evaluate the suitability of these features, simulations have been conducted using a simplified on-board power supply net as excitation source. The simulation outcome has been investigated regarding the cross correlation factor rxy and in a polynomial regression scenario. The results of the simulations show a best case error below 1 % SoC, which is 3 percentage points lower than using terminal voltage and impedance. When increasing the measurement uncertainty, the difference remains around 2 percent points.

Further improvements on the novel method for state of charge (SOC) determination of lithium iron phosphate (LFP) cells based on the impedance spectra classification are presented. A Support Vector Machine (SVM) is applied to impedance spectra of a LFP cell, with each impedance spectrum representing a distinct SOC for a predefined temperature. As a SVM is a binary classifier, only the distinction between two SOC can be computed in one iteration of the algorithm. Therefore a search pattern is necessary. A balanced tree search was implemented with good results. In order to further improvements of the SVM method, this paper discusses two new search pattern, namely a linear search and an imbalanced tree search, the later one based on an initial educated guess. All three search pattern were compared under various aspects like accuracy, efficiency, tolerance of disturbances and temperature dependancy. The imbalanced search tree shows to be the most efficient search pattern if the initial guess is within less than ±5 % SOC of the original SOC in both directions and exhibits the best tolerance for high disturbances. Linear search improves the rate of exact classifications for almost every temperature. It also improves the robustness against high disturbances and can even detect a certain number of false classifications which makes this search pattern unique. The downside is a much lower efficiency as all impedance spectra have to be evaluated while the tree search pattern only evaluate those on the tree path.

An alternative method for determining the state of charge (SOC) on lithium iron phosphate cells by impedance spectra classification is given. Methods based on the electric equivalent circuit diagram (ECD), such as the Kalman Filter, the extended Kalman Filter and the state space observer, for instance, have reached their limits for this cell chemistry. The new method resigns on the open circuit voltage curve and the parameters for the electric ECD. Impedance spectra classification is implemented by a Support Vector Machine (SVM). The classes for the SVM-algorithm are represented by all the impedance spectra that correspond to the SOC (the SOC classes) for defined temperature and aging states. A divide and conquer based search algorithm on a binary search tree makes it possible to grade measured impedances using the SVM method. Statistical analysis is used to verify the concept by grading every single impedance from each impedance spectrum corresponding to the SOC by class with different magnitudes of charged error.

In the context of transient processes in power system measurements, a sampled signal is analyzed with respect to electro-magnetic influences. These are most likely superposed sinusoids that can be found next to the fundamental system sinusoid. However, such signal is not stationary, i.e. has a varying model order which means that temporary and exponentially damped sinusoids appear eventually. In our previous work, the exponential damping was only considered indirectly but not explicitly incorporated in the signal model used. Regarding the amplitude estimation, this led to inaccuracies since the amplitude was incorrectly assumed constant within a window of samples. In this paper, we use ESPRIT's ability to also estimate a parameter of exponential damping, improve the corresponding signal model, advance the amplitude estimation algorithm and back projection algorithm. Especially short-term signal components can be tracked far more precise.

This paper investigates the impact of an error-prone buffer memory on a channel decoder as employed in modern digital communication systems. On one hand this work is motivated by the fact that energy efficient decoder implementations may not only be achieved by optimizations on algorithmic level, but also by chip-level modifications. One of such modifications is so called aggressive voltage scaling of buffer memories, which, while achieving reduced power consumption, also injects errors into the likelihood values used during the decoding process. On the other hand, it has been recognized that the ongoing increase of integration density with smaller structures makes integrated circuits more sensitive to process variations during manufacturing, and to voltage and temperature variations. This may lead to a paradigm shift from 100 %-reliable operation to fault tolerant signal processing. Both reasons are the motivation to discuss the required co-design of algorithms and underlying circuits. For an error-prone receive buffer of a Turbo decoder the influence of quantizer design and index assignment on the error resilience of the decoding algorithm is discussed. It is shown that a suitable design of both enables a compensation of hardware induced bits errors with rates up to 1 % without increasing the computational complexity of the decoder.

The development of a flexible software defined RFID is discused. Commercial reader systems only allow a top level view on the communication and restrict the variation for many transmission parameters. Recently a software reader from the CGran project was proposed which uses the GNU Radio environment in combination with an USRP front end. Because most of the signal processing is done on a common host PC, this reader offers high flexibility, but also has several disadvantages. One of the main hardware limitations is the usage of only one separated antenna per transmit and receive path. Commercial readers usually use four antennas which are time multiplexed and can be used as transmitter and receiver. In this work a HF multiplexer for the USRP device is introduced. With this extension up to four transmit and receive antennas can be used in combination with the software reader. It is shown that the multiplexer achieves good read rates for a switching interval of 100 ms. Using this multiplexer the read range of the system decrease compared to the basic software reader, but distances over two meters can still be realized without additional hardware extensions.

In the context of parameter estimation, subspace-based methods like ESPRIT have become common. They require a subspace separation e.g. based on eigenvalue/-vector decomposition. In time-varying environments, this can be done by subspace trackers. One class of these is based on the PAST algorithm. Our non-linear parameter estimation algorithm DaPT builds on-top of the ESPRIT algorithm. Evaluation of the different variants of the PAST algorithm shows which variant of the PAST algorithm is worthwhile in the context of frequency estimation.

Localization via Radio Frequency Identification (RFID) is frequently used in different applications nowadays. It has the advantage that next to its ostensible purpose of identifying objects via their unique IDs it can simultaneously be used for the localization of these objects. In this work it is shown how Received Signal Strength Indicator (RSSI) measurements at different antennae of a passive UHF RFID label can be combined for localization. The localization is only done based on the RSSI measurements and a Kalman Filter (KF). Because of non-linearities in the measurement function it is necessary to incorporate an Extended Kalman Filter (EKF) or an Unscented Kalman Filter (UKF) where simulations have shown that the UKF performs better than the EKF. Additionally to the selection of the filter there are different possibilities to increase the localization accuracy of the UKF: The advantages of using Reference Tags (RT) or more than one tag per trolley (relative positioning) in combination with an Unscented Kalman Filter are discussed and simulations results show that the localization error can be decreased significantly via these methods. Another possibility to increase the localization accuracy and in addition to achieve a more realistic simulation is the consideration of the angle between reader antenna and tag. Simulation results with the incorporation of different numbers of fixed antennae lead to the conclusion that this is a useful surplus in the localization.

This paper describes the application of an adaptive complexity decoder for the Long Term Evolution (LTE) downlink Turbo code. The proposed decoding approach is based on the block syndrome decoding principle and enables adaptive reduction of decoding effort depending on current SNR and iteration number with negligible influence on decoding performance. Numerical results in context of LTE downlink using typical mobile channels are used to demonstrate the efficiency of the approach.

In this paper blind equalization algorithms based on digital watermarking are presented. Training sequence is sent along with the data in the form of watermark. Robust CDMA based watermarking algorithm is used to watermark the data. Watermark, which is spread over the data, does not consume extra bandwidth. So with the help of extracted watermark channel can be equalized just by using simple mean square algorithm. Two algorithms for equalization are proposed in this paper. In algorithm I the receiver does not require to know training sequence in advance. Using algorithm II, the sender does not require to send training sequence either, and data can still be equalized using simple LMS algorithm at low computational complexity.

In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of many parallel implementations. However, when dealing with the parallel implementation of sparse matrix-vector multiplication (SMVM), which is the main step of all iterative algorithms for solving systems of linear equation, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using the NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have already implemented the proposed SMVM-NoC architecture with the size 4×4 and 5×5 in IEEE 754 single float point precision using FPGA.

The generalized Minimum Mean Squared Error (GMMSE) detector has a bit error rate performance, which is similar to the MMSE detector. The advantage of the GMMSE detector is that it does not require the knowledge of the noise power. However, the computational complexity of the GMMSE detector is significantly higher than the computational complexity of the MMSE detector. In this paper, the complexity of the GMMSE detector is reduced by taking into account the structure of the system matrix (Toeplitz). Furthermore, by using circular approximation of the structured system matrix an approximate GMMSE detector is presented, whose computational complexity is only slightly higher than MMSE, i.e.~only an iterative gradient descent algorithm based on the inversion of diagonal matrices is additionally required.

Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

Today Discrete Fourier Transforms (DFTs) are applied in various radio standards based on OFDM (Orthogonal Frequency Division Multiplex). It is important to gain a fast computational speed for the DFT, which is usually achieved by using specialized Fast Fourier Transform (FFT) engines. However, in face of the Software Defined Radio (SDR) development, more general (parallel) processor architectures are often desirable, which are not tailored to FFT computations. Therefore, alternative approaches are required to reduce the complexity of the DFT. Starting from a matrix-vector based description of the FFT idea, we will present different factorizations of the DFT matrix, which allow a reduction of the complexity that lies between the original DFT and the minimum FFT complexity. The computational complexities of these factorizations and their suitability for implementation on different processor architectures are investigated.

In this paper a computationally efficient and high-quality preserving DCT architecture is presented. It is obtained by optimizing the Loeffler DCT based on the Cordic algorithm. The computational complexity is reduced from 11 multiply and 29 add operations (Loeffler DCT) to 38 add and 16 shift operations (which is similar to the complexity of the binDCT). The experimental results show that the proposed DCT algorithm not only reduces the computational complexity significantly, but also retains the good transformation quality of the Loeffler DCT. Therefore, the proposed Cordic based Loeffler DCT is especially suited for low-power and high-quality CODECs in battery-based systems.

Convolutional codes, which are frequently used as error correction codes in digital transmission systems, are generally decoded using the Viterbi Decoder. On the one hand the Viterbi Decoder is an optimum maximum likelihood decoder, i.e. the most probable transmitted code sequence is obtained. On the other hand the mathematical complexity of the algorithm only depends on the used code, not on the number of transmission errors. To reduce the complexity of the decoding process for good transmission conditions, an alternative syndrome based decoder is presented. The reduction of complexity is realized by two different approaches, the syndrome zero sequence deactivation and the path metric equalization. The two approaches enable an easy adaptation of the decoding complexity for different transmission conditions, which results in a trade-off between decoding complexity and error correction performance.

This paper presents two Cordic based algorithms which may be used for digital baseband processing in OFDM and/or CDMA based communication systems. The first one is a linear least squares based multiuser detector for CDMA incorporating descrambling and despreading. The second algorithm is a pure Cordic based FFT implementation. Both algorithms can be implemented using solely Cordic based architectures (e.g. coprocessors or ASIPs). The algorithms exactly fit the needs of a multistandard terminal as they both are freely parameterizable. This regards to the accuracy of the results as well as to the parameters of the performed function (e.g. size of the FFT).

Using adiabatic CMOS logic instead of the more traditional static CMOS logic can lower the power consumption of a hardware design. However, the characteristic differences between adiabatic and static logic, such as a four-phase clock, have a far reaching influence on the design itself. These influences are investigated in this paper by adapting a systolic array of CORDIC devices to be implemented adiabatically. We present a means to describe adiabatic logic in VHDL and use it to define the systolic array with precise timing and bit-true calculations. The large pipeline bubbles that occur in a naive version of this array are identified and removed to a large degree. As an example, we demonstrate a parameterization of the CORDIC array that carries out adaptive RLS filtering.

Multi-user detection is a technique proposed for mobile radio systems based on the CDMA principle, such as the upcoming UMTS. While offering an elegant solution to problems such as intra-cell interference, it demands very significant computational resources. In this paper, we present a high-level approach for reducing the required resources for performing multi-user detection in a 3GPP TDD multi-user system. This approach is based on a displacement representation of the parameters that describe the transmission system, and a generalized Schur algorithm that works on this representation. The Schur algorithm naturally leads to a highly parallel hardware implementation using CORDIC cells. It is shown that this hardware architecture can also be used to compute the initial displacement representation. It is very beneficial to introduce incremental refinement structures into the solution process, both at the algorithmic level and in the individual cells of the hardware architecture. We detail these approximations and present simulation results that confirm their effectiveness.