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The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. The lifetime of up- and downstream test structures with different overlaps as well as strong misalignment was determined by measurements. Investigations have shown that the alignments have a noticeable effect on the reliability and performance of test structures. The downstream line shows the expected lifetime behavior. For the upstream line no influence of the misalignment on the lifetime was found. Simulations are taken into account to understand the thermal–electrical and mechanical behavior.

Robust metallizations for harsh environment and high current applications in integrated circuits are required for automotive or industrial applications. To achieve a higher current capability so called “power metals” are used. The new concept of slotted geometries shows a better robustness towards degradation due to electromigration. This is a new design concept which is contrary to the conventional concept to use homogeneous filled metal tracks. A reliability investigation of octahedron-shaped slots in metal tracks was carried out by dynamic simulations. The determination thermal–electrical–mechanical behaviour was simulated with the finite element software ANSYS®.

At the moment the miniaturisation of integrated circuits for consumer electronics means to decrease the size of Cu interconnects below 100 nm, while a lifetime of 3–5 years has to be guaranteed. For industrial and automotive applications wider Al interconnects (∼350 nm) are used, but an extreme low rate of failures (0.1 ppm) has to be reached to produce reliable end-products including dozens of components. A further progress in the development of high-end electronics and more complex industrial products needs a better prediction of possible failure mechanism and the related time to failure of the chosen technology. This investigation is focused on migration induced void formation and combines the results of process simulations, for the back end of line, (intrinsic pre-stress) with the dynamic simulation of the migration induced material movement in the interconnects. To minimise the gap between idealized simulations and reliability tests the grain structure of the Al and Cu lines, the interaction between electromigration and the mass flux due concentration gradients, as well as the different transport mechanism for grain boundary and interface diffusion were taken into account. For the surrounding metal of existing voids specific activation energies in dependence on the crystal orientation of the metal surfaces were given. As result a prediction of the point of failure and the void formation process will be given for the chosen back-end technologies.

For industrial and automotive applications a 0.35μm aluminium CMOS process is one of the common used technologies. An increasing demand on extended operating conditions must be fulfilled especially for high current carrying metal lines. A new design concept is to modify the shape of these lines. The use of slots especially of octahedron slots demonstrates a better robustness towards electromigration in upper metallization layers. Another benefit is the good reliability under pulsed DC conditions primarily in comparison to wide homogeneous filled metal lines. In addition with slotted metal in all metallization layers stress due to thermal expansion can be reduced by keeping the lifetime at an adequate level. The performance of different layouts were investigated by electromigration tests and simulation to prepare basis knowledge for decision making process for design for higher robustness.

The main trends in consumer electronics are increasing performances of their products and a reduction of the costs. These trends lead to an ongoing integration on package level which leads to a decreasing size of the solder contacts. This goes along with a higher sensibility to thermal-mechanical stress and void formation due to electromigration (EM). Against this background copper pillar bumps were introduced, because they combine the robustness of metal wire bonds with the low bonding pressure of reflow soldering. Experimental results have shown a longer lifetime of Cu pillar bumps during EM tests, but a continuative analysis is still needed for design optimization. Against this background a finite element analysis (FEA) was performed to compare the EM induced mass flux in conventional solder bumps and in two different designs for Cu pillar bumps. The thermal electrical simulations were performed with ANSYS®. Afterwards a user routine was used to calculate the EM induced mass fluxes and mass flux divergences. The simulation results are used to identify possible reasons for the increased EM performance of Cu pillar bumps and they enable the identification of preferable designs.

The development of 3D-silicon integrated circuits is an increasing demand especially regarding to advanced 3D-packages and high performance applications, with the intend to miniaturize and to reduce costs. Through-silicon-vias (TSV), interconnects and landing pads have a strong mismatch in proportions. Due to high temperature as well as high applied currents, the reliability of the systems and components is affected by thermal and thermal-electrical loads. The induced stress leads to degradation effects like electro- and thermomigration (EM, TM). Mismatch in coefficient of thermal expansion (CTE) are causing mechanical induced stress during the manufacturing process. This can lead to failure mechanisms like delamination and cracking around the TSV or in the ICs.

Due to the miniaturization process of the CMOS components metallization structures are becoming more and more complex. Better knowledge to improve via robustness for high current applications is needed. Geometry changes can have a big effect on the physical behaviour. For higher robust metallization systems it is necessary to learn more about overlap design to meet the most economic layout. Slotted high current line layouts do not allow the use of big via areas. Furthermore the number of vias increases the resistance. Investigations have shown the existence of an optimal overlap.

The advantage of an increased lifetime of slotted metal tracks for the use in integrated circuits has already been shown. A benefit for slotted metal track geometries especially for thick metal tracks under DC and DC pulsed stress test conditions could be confirmed by lifetime measurements. To achieve a higher current capability these metal tracks, also known as “power metals”, were used in upper metallization layers. This new design concept shows a better robustness towards electromigration in comparison to conventional wide unslotted metal tracks. A new concept deals with the use of slotted geometries in lower metallization layers. Simulations show a decrease of von Mises stress in comparison to unslotted metal tracks. This behaviour can reduce the current shift of active and passive devices due to the imposed stress of the lower metallization layers.

For high temperature automotive applications a 0.35 μm aluminium CMOS is one of the common technology processes. In this process Ti/Al/Ti/TiN stacks are used as metallization. These aluminium stacks form TiAl3 layers during the following annealing step. The thermal-electrical and thermo-mechanical properties of this metallization is different from titanium or aluminium. Hence the forming TiAl3 layer influences the thermalelectrical, thermo-mechanical behaviour and reduces the current capability. The influence of the deposition temperatures on the thermal-electrical behaviour is investigated. Three different deposition temperatures of 150 °C, 250 °C and 470 °C were considered. Also the behaviour of anisotropic etching was investigated with regard to the reduced current capability.

Highly robust metallizations in ICs for high temperature and high current applications are needed. Special thick metal layers often known as “power metals” are added to achieve a higher current capability. But these metallizations suffer from reliability limitations as well. Therefore a new design for “power metals” was created for a 0.35μm aluminium CMOS process. The reliability of a new power metal structure is investigated in this article. A determination of the thermal-electrical and thermo-mechanical behaviour is carried out by simulations.

Embedding passives in PCB permits to gain in integration density while enhancing electromagnetic compatibility performances. The choice of the dielectric film is fundamental for large frequency band stability of embedded capacitances. However, these materials are prone to water absorption, which can lead to functional parameter degradations and additional stresses at the interfaces. This paper presents experimental capacitors embedded in FR-4, and finite element simulations of moisture absorption in various dielectric materials. Technological choices, as well as the qualification procedure, can be improved thanks to the simulation results.