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Spiking neural networks (SNNs) are artificial neural network models that more closely mimic biological neural networks. In addition to neuronal and synaptic state, SNNs incorporate the variant time scale into their computational model. Since each neuron in these networks is connected to thousands of others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, very low communication latency is also needed. The 2D-NoC was used as a solution to provide a scalable interconnection fabric in large-scale parallel SNN systems. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. The combination of these two emerging technologies provides a new horizon for IC designs to satisfy the high requirements of low power and small footprint in emerging AI applications. In this work, we first present a comprehensive analytical model to analyze the performance of 3D mesh NoC over variants of different SNN topologies and communications protocols. Second, we present an architecture and a low-latency spike routing algorithm, named shortest path K-means based multicast (SP-KMCR), for three-dimensional NoC of spiking neurons (3DNoC-SNN). The proposed system was validated based on an RTL-level implementation, while area/power analysis was performed using 45nm CMOS technology.

As 2-D CMOS reaches its fundamental scaling limits due to device, manufacturing, and interconnect bottleneck related constraints at the nanoscale, migration to 3-D provides a possible alternative to continue technology scaling in future. Toward that goal, several 3-D integration approaches with multi-die, multichip, and sequential layers stacking are pursued. However, these approaches only show incremental density benefits and exhibit new challenges, such as lack of thermal management, increasing cost, and reliability issues. In contrast to these, we proposed a radically different fabric concept, called stacked horizontal nanowire-based 3-D CMOS (SN3D), on a single die that can offer a paradigm shift in technology scaling as well as design. Using prefabricated and doped stacked horizontal nanowires as fundamental building blocks, the fabric is assembled using architected connectivity and insulation features. Innovations in circuit style for mapping to SN3D’s physical framework, and bottom-up material filling-based manufacturing techniques are also central to our approach. In this paper, we detail, fabric’s core constructs, logic circuits implementation in SN3D fabric, benchmarking methodology and results, and finally the manufacturing aspects. Our circuit analysis reveals tremendous benefits; for a 4-bit full adder design, SN3D shows $11\times $ , 19%, 18%, and 6.7 $\times $ , 8.69%, 9% benefits over state-of-art 2-D CMOS and transistor-level monolithic 3-D in terms of density, power, and performance, respectively. In addition, our step-by-step TCAD emulation of manufacturing flow establishes feasibility. If realized, the SN3D fabric can be transformative for the semiconductor industry.

Spiking Neuromorphic systems have been introduced as promising platforms for energy-efficient spiking neural network (SNNs) execution. SNNs incorporate neuronal and synaptic states in addition to the variant time scale into their computational model. Since each neuron in these networks is connected to many others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, a precise communication latency is also needed, although SNN is tolerant to the spike delay variation in some limits when it is seen as a whole. The two-dimensional packet-switched network-on-chip was proposed as a solution to provide a scalable interconnect fabric in large-scale spike-based neural networks. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. Combining these two emerging technologies provides a new horizon for IC design to satisfy the high requirements of low power and small footprint in emerging AI applications. Moreover, although fault-tolerance is a natural feature of biological systems, integrating many computation and memory units into neuromorphic chips confronts the reliability issue, where a defective part can affect the overall system's performance. This paper presents the design and simulation of R-NASH-a reliable three-dimensional digital neuromorphic system geared explicitly toward the 3D-ICs biological brain's three-dimensional structure, where information in the network is represented by sparse patterns of spike timing and learning is based on the local spike-timing-dependent-plasticity rule. Our platform enables high integration density and small spike delay of spiking networks and features a scalable design. R-NASH is a design based on the Through-Silicon-Via technology, facilitating spiking neural network implementation on clustered neurons based on Network-on-Chip. We provide a memory interface with the host CPU, allowing for online training and inference of spiking neural networks. Moreover, R-NASH supports fault recovery with graceful performance degradation.

International audience; Processing information with conventional integrated circuits remains beset by the interconnect bottleneck: circuits made of smaller active devices need longer and narrower interconnects, which have become the prime source of power dissipation and clock rate saturation. Optical interchip communication provides a fast and energy-saving option that still misses a generic on-chip optical information processing by interconnect-free and reconfigurable Boolean arithmetic logic units (ALU). Considering metal plasmons as a platform with dual optical and electronic compatibilities, we forge interconnect-free, ultracompact plasmonic Boolean logic gates and reconfigure them, at will, into computing ALU without any redesign nor cascaded circuitry. We tailor the plasmon mode landscape of a single 2.6 μm2 planar gold cavity and demonstrate the operation and facile reconfiguration of all 2-input logic gates. The potential for higher complexity of the same logic unit is shown by a multi-input excitation and a phase control to realize an arithmetic 2-bit adder.

The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer. A cryogenic CMOS control chip operating at 3 K is used to demonstrate coherent control and simple algorithms on silicon qubits operating at 20 mK.

Golden Moore predicted that the number of transistors in an integrated circuit doubles every 18 months. This law is known as Technology Growth Law. Now, Moore’s law reaches saturation due to manufacturing, materials, and design limitations. New trends have been proposed to evade Moore’s law. Here we will present the parallel computing. Parallel computing/programming is a computer programming technique that enables parallel execution of operations. It uses multiple processors in parallel to solve problems more quickly than with a single processor. If you cannot increase the clock, do more operations by one clock. But, we cannot build an infinite processor due to temperature, cooling problems, interconnect bottleneck, etc. [1–5]. Performance gained by multicore processor strongly dependent on the software algorithms and implementation. Moore’s law continues to provide more transistors, but threshold, and thus supply voltages no longer scale down each generation. Hence, to leverage the additional transistors, designers reduce clock frequency and invest the power headroom to activate twice as many cores. Because of the quadratic relationship between power and voltage, a small voltage/frequency reduction allows a doubling of the number of transistors that switch each cycle, enabling overall throughput improvements from multicore. We cannot just reduce the size of transistors to improve performance as smaller transistors → faster processors → increased power consumption → increased heat → unreliable processors. Parallel computing applications include

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.

Graphene with significant potentials in diverse areas of physical and biological sciences is proposed as a solution to complementary problems of semiconductor and biomedical industries, i.e., the on-chip (OC) interconnect bottleneck and in-body (IB) wireless communications/power transfer (PT), respectively. Emerging nanoscale solutions with radio frequency, optical, ultrasonic, or molecular channels in OC and IB media have various challenges including achievable footprints and frequency, energy consumption, medium dependent features, and interference. In this paper, major challenges are addressed with magneto-inductive (MI) transceivers by combining the advantages of THz operation frequency, unique features of intercalated multi-layer graphene (MLG) coils and range extension with MI waveguides. Our design promises scalable and high performance solutions for the OC interconnect bottleneck while providing biocompatible and universal solutions for challenging IB medium. The proposed solution is theoretically analyzed and numerically compared with the copper-based alternatives, and the practical challenges are discussed. Simulation results achieve high capacity (several Tbit/s) and ultra-low power (500 zJ/bit) wireless communications while providing high (hundreds of kWs) and efficient (109 W/mm2) wireless PT at several millimeters. In addition, unique properties of MLG such as lightweight structure, biocompatibility, current carrying capacity, and planar manufacturability make the solution more promising for challenging environments.

Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/output (I/O) connectors present in cryostats operating at sub-kelvin temperatures required to execute quantum logic with high fidelity. This interconnect bottleneck is equally present in the device fabrication-measurement cycle, which requires high-throughput and cryogenic characterization to develop quantum processors. Here we multiplex quantum transport of two-dimensional electron gases at sub-kelvin temperatures. We use commercial off-the-shelf CMOS multiplexers to achieve an order of magnitude increase in the number of wires. Exploiting this technology, we accelerate the development of 300 mm epitaxial wafers manufactured in an industrial CMOS fab and report a remarkable electron mobility of (3.9 ± 0.6) × 105 cm2/Vs and percolation density of (6.9 ± 0.4) × 1010 cm−2, representing a key step toward large silicon qubit arrays. We envision that the demonstration will inspire the development of cryogenic electronics for quantum information, and because of the simplicity of assembly and versatility, we foresee widespread use of similar cryo-CMOS circuits for high-throughput quantum measurements and control of quantum engineered systems.

Just as classical information technology rests on a foundation built of interconnected information-processing systems, quantum information technology (QIT) must do the same. A critical component of such systems is the interconnect, a device or process that allows transfer of information between disparate physical media, for example, semiconductor electronics, individual atoms, light pulses in optical fiber, or microwave fields. While interconnects have been well engineered for decades in the realm of classical information technology, quantum interconnects (QuICs) present special challenges, as they must allow the transfer of fragile quantum states between different physical parts or degrees of freedom of the system. The diversity of QIT platforms (superconducting, atomic, solid-state color center, optical, etc.) that will form a quantum internet poses additional challenges. As quantum systems scale to larger size, the quantum interconnect bottleneck is imminent, and is emerging as a grand challenge for QIT. For these reasons, it is the position of the community represented by participants of the NSF workshop on Quantum Interconnects that accelerating QuIC research is crucial for sustained development of a national quantum science and technology program. Given the diversity of QIT platforms, materials used, applications, and infrastructure required, a convergent research program including partnership between academia, industry and national laboratories is required. This document is a summary from a U.S. National Science Foundation supported workshop held on 31 October - 1 November 2019 in Alexandria, VA. Attendees were charged to identify the scientific and community needs, opportunities, and significant challenges for quantum interconnects over the next 2-5 years., Comment: This is an updated version V2, including expanded text and listing of all co-authors. To whom correspondence should be addressed: Marko Lon\v{c}ar: loncar@seas.harvard.edu; Michael G. Raymer: raymer@uoregon.edu

In order to prolong the lifetime of Cu as an interconnect metal in CMOS devices, as transistors continue to decrease in size, materials that combine properties of diffusion barriers and seed liners are needed. Such a material will have to allow for successful electroplating of Cu and must be as thin as possible in order to facilitate the coating of high-aspect ratio interconnect vias. One possible way to achieve such a material is presented in this study. Through density functional theory we investigate the behaviour Cu on Ru-doped and Ru passivated ε-TaN (1 1 0). Adsorption and diffusion of one and two Cu atoms on these surfaces were studied initially, in order to understand the early stages of film growth. This showed that while adsorption and surface diffusion were more favourable on the Ru passivated surface, Ru dopants act as a nucleation site for Cu atoms and enhance the metal-surface interaction. To understand the growth mechanism of Cu films on these surfaces in more detail, and to discover the optimum Ru content for the surface, large Cu sheets are adsorbed to the Ru passivated surface as well as to Ru-doped surfaces with a variety of surface doping concentrations. On the Ru-doped films, Cu spontaneously transitions into a two-layer structure, while atoms remain in a single layer on the Ru-passivated surface. However, ab initio molecular dynamics and activation energies of pathways for migration of atoms to form further layers show that the Ru dopants inhibit further 3D growth of the Cu structures.

Interconnect opens are a major class of defects found in today’s nanometer technologies. These defects present subtle behavior that could lead to test escapes and hence compromise test quality. Furthermore, they could become a reliability risk. Low-voltage testing has been suggested as a static test to improve the defect coverage of interconnect opens. In nanometer technologies, process variability is predominant and considering only the nominal value of parameters is not realistic. Hence, process variations should be considered to analyze the behavior of interconnect opens. In this brief, the detection capabilities of low-voltage testing for interconnect opens considering process variations is investigated. A statistical model is used for the interconnect open defect. Correlation between parameters of the affected gates and spatial correlation of the parameters for those gates tied to the defective floating node have been considered. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. Based on these results, it is suggested to use low $V_{\rm DD}$ in conjunction with favorable logic conditions at the coupling lines to enhance the defect coverage of interconnect opens leading to better test quality and higher product reliability.

With ever decreasing transistor size, materials that combine both diffusion barrier and liner material properties are needed to successfully electroplate Cu and thus beat the current interconnect bottleneck. In order to facilitate coating of high aspect ratio vias, the material should be as thin as possible. One possibility to achieve this is presented in this study, where we investigate through density functional theory, the behavior Cu on Ru-doped and Ru passivated ε-TaN (1 1 0). Initially, the adsorption, diffusion and association of one and two Cu atoms on the different surfaces was studied in order to probe the early stages of film growth. This showed that, while surface diffusion of atoms was more favourable on the Ru-passivated surface, the Ru dopant acts as a nucleation site for Cu, with atoms preferentially diffusing towards it. In order to understand the mechanism of film growth on this surface in more detail and to fine-tune the barrier and liner properties of the material, the effect of different percentages of surface doping were studied. Further, the behavior of Cu13 and Cu29 clusters on different doped surfaces and on the passivated surfaces was investigated. In particular, the study focused on the pathways toward agglomeration as well as the associated activation energies. We find that on a Ru doped surface the atoms agglomerate spontaneously to form a two-layer film, whereas they remain in a monolayer on Ru-passivated TaN (1 1 0).

Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Thus, the focus is on optimizing interconnect parasitics in order to achieve optimum performance. The increased total device capacitance and the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. In this paper, the impact of interconnect resistance on the circuit performance is weighed against interconnect capacitance, and less aggressive wire width and thickness scaling are proposed. This analysis is carried out based on the results from fully timing-closed, GDSII-level layout of circuit blocks, for the 11- and 7-nm technology nodes. The sensitivity of circuit power dissipation and signal noise to interconnect dimensions is assessed in detail. This approach compromises wire capacitance and gradually renders it important in circuit delay. The circuit performance enhancement by air-gap (AG) interconnect technology is studied with the traditional BEOL scaling versus the proposed wire sizing. It is found that using the latter wire sizing approach with air-gap interconnects is more beneficial to circuit performance.

Reduction of interconnect delay and interconnect power has become a primary design challenge in recent CMOS technology generations. Spacing between wires can be modified so that line-to-line capacitances will be optimized for minimal power under timing constraints. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing that minimizes the total dynamic power dissipation caused by an interconnect, while maximum delay constraints are satisfied. A multi-dimensional visibility graph is used to represent the problem, and a layout partitioning technique is applied to solve the problem efficiently. The algorithm was evaluated on an industrial microprocessor designed using the 32nm technology, and it achieved a 5-12% reduction in interconnect switching power. Multi-layer interconnect power optimization under timing constraints is described.Related global optimization problem is formulated.An algorithm for solving optimization problem is described and implemented.A mathematical relation to similar optimization problems is developed.5-12% dynamic interconnect power reduction on industrial cases is demonstrated.

Near-infrared nanophotonics has been massively studied due to its promising ability in addressing the interconnect bottleneck problem [1] and achieving resonator-based sensors with high quality factor [2] [3]. Among the various material platforms that have been applied in near infrared nanophotonics, silicon-on-insulator (SOI) platform offers advantages such as high optical mode confinement, low loss, CMOS compatibility, and mature fabrication [4].

CMOS scaling faces numerous challenges, among which device scaling, interconnect bottleneck, high leakage power and manufacturability are major ones. The scaling challenge is particularly acute for SRAM since maximum performance/power at highest density is required with every new generation. 3-D integration provides possible pathways to overcome the impediments faced in achieving ultra-high density SRAM. However 3-D integration techniques like monolithic 3-D, die-die [6-11][14-18], etc., show limited benefits and add additional constraints. Stacked Horizontal Nanowire-based 3-D CMOS (called SN3D hereafter)[19][20] is a true fine-grained 3-D IC fabric that can solve CMOS scaling challenges while providing significantly higher density, routability, performance/power advantages. Central to our approach is the formation of the device and routing structures onto stacked horizontal nanowires, and design and placement of symmetric CMOS circuits in 3-D. In this paper, we show design and analysis of SRAM circuit in SN3D and benchmark its potentials. We detail circuit design and implementation procedures considering underlying physical fabric. We analyze SRAM performance metrics: read, write, hold stability and performance margins, and compare the results with 2-D CMOS and Monolithic 3-D. Our simulation results showed 3.1x density, and 6.4x performance/watts benefits with respect to 2-D CMOS and 2.1 density and 5.7x performance/watts benefits over monolithic 3-D at 16nm. We have also achieved 1.7x Hold Margin (HM), 4.3x Read Margin (RM) and 1.2x Write Margin improvements over 2-D CMOS and monolithic designs.

Interconnects are increasingly contributing to the overall delay at advanced technology nodes. It is becoming increasingly important to study the dynamics between the transistor and interconnect parasitics, and optimize interconnect geometries for every device option to enable optimum performance and power. Prior work has shown that interconnect resistance becomes more important than interconnect capacitance in the FinFET technology era. It is shown that with new transistor innovations like FDSOI, and the TFET technology, the implications on the BEOL design paradigm is contrasting to the prior findings with the FinFET technology. For devices like TFET, which are highly resistive, and have low device capacitance, the circuit delay can be improved by sizing interconnects to have lower capacitance, at the cost of higher resistance.

Today's computing systems suffer from a memory/communication bottleneck, resulting in high energy consumption and saturated performance. This makes them inefficient in solving data-intensive applications at reasonable cost. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor crossbar technology, offers a potential solution to the memory bottleneck. An efficient interconnect network is essential to maximize CIM's architectural performance. This paper presents three interconnect network schemes for CIM architecture; these are (1) CMOS-based, (2) memristor-based and (3) hybrid cmos/memristor interconnect network scheme. To illustrate the feasibility of such schemes, a CIM parallel adder is used as a case study. The results show that the hybrid interconnect network scheme achieves a higher performance in comparison with the CMOS-based and memristor-based interconnect scheme in terms of delay, energy and area.

In modern IC chips, on chip interconnects plays a dominant role because of the device parasitic's. Several analytical and mathematical models are used for the interconnect analysis for delay reduction. But with the technology scaling towards nanometers, interconnect length is increasing exponentially. So, more accurate and efficient techniques for interconnect analysis are essential to reduce the propagation delays and increase the overall circuit performance in-terms of speed. Here a new interconnect scheme based on the transmission line model is proposed. This interconnect scheme has a resistance and conductance at the input, output and a lossless T-type LC network between them. Closed form delay model of interconnect is developed, which is a third order approximation to achieve better accuracy and less delays. The lumped delay models such as RC, RLC and RLGC are compared with the proposed model of interconnect for performance analysis in-terms of propagation delays and average power. The comparison analysis have shown that the proposed model of interconnect has less transients, average and propagation delays when compared to the other delay models.

Major obstacles in current CMOS technology, such as the interconnect bottleneck and thermal heat management, can be overcome by employing subwavelength-scaled light in plasmonic waveguides and devices. In this work, a plasmonic structure that implements the majority (MAJ) gate function is designed and thoroughly studied through simulations. The structure consists of three merging waveguides, serving as the MAJ gate inputs. The information of the logic signals is encoded in the phase of transmitted surface plasmon polaritons (SPP). SPPs are excited at all three inputs and the phase of the output SPP is determined by theMAJof the input phases. The operating dimensions are identified and the functionality is verified for all input combinations. This is the first reported simulation of a plasmonic MAJ gate and thus contributes to the field of optical computing at the nanoscale. (C) 2017 Author(s).

Exploiting the advantages of 3-D integration requires the development of novel circuit architectures. A 3-D version of a microprocessor memory system is a primary example of the architectures discussed in this chapter. Major improvements in throughput, power consumption, and cache miss rate are demonstrated. Communication centric architectures, such as a network-on-chip, are also discussed. On-chip networks are an important design paradigm to appease the interconnect bottleneck, where information is communicated among circuits within packets in an Internet-like fashion. The synergy between these two design paradigms, networks-on-chip and 3-D, to significantly improve performance while decreasing the power consumed in communications limited systems is described.

As the technology scales down to the sub-10 nm nodes, the interconnect performance becomes primarily dominated by the resistance rather than the capacitance due to the ever-increasing size effects of copper and a higher input capacitance of the devices. The implications of this paradigm shift are discussed in this letter, and it is shown that the local interconnect technology needs to be reoptimized to rebalance the interconnect resistance and capacitance. One approach is to increase the interconnect width beyond half pitch without changing the interconnect pitch. For the 5-nm technology node with an aspect ratio of 3, the energy-delay product of vertical field-effect transistor circuits at the optimal relative width improve up 55%, compared with the circuits using an aspect ratio of 2 and an interconnect width of half pitch.

In this paper, four types of on-chip point-to-point communication links are optimized for low energy per bit at sufficient bandwidth density for use in high performance applications: on-chip optical interconnect links with off-chip and with on-chip lasers, electrical full-swing RC links and electrical transmission line (TL) links. System requirements and interconnect link performance are evaluated based on the ITRS scaling roadmap. A benchmark of the link performance against system requirements indicates that full-swing RC interconnect suffices down to 12nm. Both TL and optical interconnect can provide low-latency communication with sufficient bandwidth density and sufficiently low energy per bit until the end of the roadmap. For the system scenario studied in this work, there is no evident need to switch to the optical option.

Parasitic elements play a major role in advanced circuit design and pose considerable run-time and memory problems for the post-layout verification, especially in the case of full-chip extraction. This brief presents a realizable R(L)C(M)-netlist-in-R(L)C(M)-netlist-out method to sparsify and reduce the capacitive coupling parasitics in circuits with interconnect lines. The method is applicable in conjunction with partitioning-based model-order reduction algorithms to reduce the complete extracted netlists, or as a stand-alone tool to process only the capacitive coupling. It is shown that, by using the method, circuits with even dense capacitive coupling can be partitioned and reduced efficiently.

paper presents an effective approach to estimate tree interconnect delays in VLSI circuit designs in deep submicron technologies at high frequencies. In this paper, a symmetrical multi-level interconnect tree network topology has been taken up which consists of elementary resistance, inductance in series with capacitance in parallel. A precise method of modeling symmetrical T-tree interconnect network is effectively examined in this paper. By moment matching fine results are obtained at frequencies as high as 2 GHz at 180 nm technology node.

Interconnects are integral part in the chip design which plays a major role in circuit performance in DSM technology. Due to the presence of parasitic such as Resistance, Capacitance components, signal degradation and delayed problems may occur. Now days because of technological advances, number of nodes increasing in circuits, there by introducing more parasitic in multi nodes which will effect on the circuit performance in terms of delay and power. With this motivation, here we have presented simulation analysis of the effect of interconnects due to parasitic and load on the circuit performance parameters in various DSM technologies. All simulations have done by considering the simple RC interconnect with a driver and load concepts. For the simulated interconnect model with variable lengths, delay and PDP values are estimated. The performance metrics indicates, there is a liner increment with change in load, 5 to 10% variations in same technology for variable lengths of interconnect and 40 to 50% variation in different technologies.

This paper describes a fast interconnect scheme and the optimized circuit for FPGA programmable interconnects to achieve great performance and static power reduction. The fast interconnect scheme including fast connection between logic blocks and optimization of wire segments are proposed to reduce path delay and increase connectivity. Furthermore, non-minimum channel length technology is applied to routing circuits, which could effectively reduce static power dissipation. Experimental results show the optimized interconnect scheme can achieve 33.1% improvement of speed in average. With the optimization of non-minimum channel length technology, interconnect circuit can reduce up to 37.4% static power dissipation and even remain the speed.

Photonics implemented in unmodified microelectronics CMOS has the potential to resolve the microprocessor to memory interconnect bottleneck that restricts the performance of modern computers. Here, we review the development of a dual-core microprocessor with monolithically embedded, energy-efficient photonics that provides direct connection to memory.

Modern microprocessors performance is often limited by the data delivery rate through conventional electrical interconnects. Optical interconnects offer a viable path to relieving this interconnect bottleneck and significantly increasing the capability of modern computers and datacenters. Here, we present a model and experimental validation for the high-speed performance of CMOS optical modulators using interleaved junctions. This model is benchmarked against two generation of CMOS modulators. The model uncovers the underlying bandwidth limitations of existing devices and suggests improvements that would enable 35 GHz optical modulators in microelectronics CMOS.

The Interconnect topology is one of the key design choices of large-scale distributed computer architectures. It might also become one of the most power consuming design elements as traffic volumes and interconnect size continue to grow. High interconnect power consumption can be simply provoked by non-energy efficient components, or can in contrast be due to architectural misconception. In this paper, we propose and combine various high-level models to realize a clear breakdown of the power consumptions, and analyze how these depend on various parameters, either external or internal, to the interconnect. Our initial results indicate that end-to-end interconnect consumption is dominated by routers. The node compute power can also affect the interconnect energy efficiency, especially if links of equal bandwidth are used as injection links and topology inner links.

The development of accurate diagnosis methodologies is important to identify process problems and achieve fast yield improvement. As open defects are becoming dominant in some CMOS technologies, their accurate diagnosis is key to improving the quality of new very large-scale integrated circuits. Widely used interconnect full open diagnosis procedures are based on the assumption that neighboring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, where the influence of transistor capacitances is significant. This paper presents a diagnosis methodology for interconnect full open defects which considers and models the impact of transistor parasitic capacitances on the defective node accurately. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behavior. Diagnosis results for real defective devices from different technology nodes are also provided.

In the conventional scaling scheme, interconnect delay cannot be reduced and the global interconnect delay become worse if the length of the wire is not scaled. The conventional approaches of global interconnect design are (1)introduction of inverse scaling concept where the upper metal layers have larger cross sections than lower metal layers, (2)insertion of repeaters, and (3) architecture level approach of multi/many core. In order to improve global interconnect delay even in aggressively miniaturized circuit, we have developed the transmission lien interconnect. This paper describes the novel analytical interconnect length distribution and discussion on future interconnect design direction. Then, recent our developments of the transmission line interconnect are described and performance comparison with another global wiring scheme such as optical interconnection is discussed.

This paper presents an interconnect resilient (IR) methodology with maximal interconnect fault tolerance, yield, and reliability for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in an interconnect structure, this method can tolerate faulty connections by efficiently finding alternative paths. The proposed approach is compatible with previous interconnect detection and diagnosis methods under oscillation ring schemes, and together they can be applied to implement a robust interconnect structure that may still provide correct communication even under multiple link faults in Network-on-Chips (NoCs). With such knowledge, designers can significantly improve interconnect reliability by augmenting vulnerable interconnect structures in NoCs. As a result, the experimental results show that alternative paths in NoCs can be found for almost all paths. Hence, the proposed method provides a good way to achieve fault tolerance and reliability/yield improvement.

With the rising cost of Au base material, many power semiconductor device manufacturers are evaluating alternative interconnect technologies to reduce manufacturing costs. In addition, shrinking package sizes, increasing electrical performance requirements and environment-friendly packaging objectives are additional considerations when choosing an alternative interconnect technology. Presently, three primary technologies compete to become the dominant Au wire replacement in the small outline, discrete power semiconductor market. Each alternative, Cu Wire, Cu Clip, and Al Ribbon, attempts to strike the best balance of electrical performance, manufacturing cost, and production yield. The small outline, discrete power semiconductor market can be broadly described as the sub-category of discrete semiconductors presently utilizing multiple 2-mil (or larger) diameter Au ball bonds as the interconnect between the die and the package leads. This paper explores observed benefits of these competing technologies in two example Power SO-8 packages that are presently ball-bonded with 2-mil Au Wire. In this comparison, we will examine the electrical performance (Rds(on) reduction), reported productivity (UPH), production yields, manufacturing cost-per-part, product-line flexibility and lead-free compliancy for each interconnect method. From this case study, similar extrapolations can be made for applying these interconnect technologies to similar packages, such as Small Outline Non-leaded (SON or PDFN), Power QFNs (PQFN), Driver MOSFETs (DrMOS), and Bi-Polar Transistor packages.

Integrated circuit (IC) reliability is gaining increasing concerns in IC technology with decreasing device size, and the impact of interconnect failure mechanisms on IC failure rate increases significantly with decreasing interconnect dimension and increasing number of interconnect levels. In this work, we attempt a first step in the study of interconnect electromigration reliability in integrated circuit using a complete 3D circuit model. 3D circuit model is necessary because all integrated circuits are 3D in their actual physical implementation, and 3D model is essential for the study of today interconnect reliability. As temperature and stress distributions in the interconnect are crucial to its reliability, we demonstrate our method through the computation of their distributions in a simple inverter circuit under typical normal operating condition, and the locations of the electromigration weak spots in the interconnect system are identified.

Power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. While most analyses focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model [1]. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. Categories and Subject Descriptors B.7.2 [ Integrated Circuits ]: Design Aids – Simulation; General Terms Algorithms, Design, Theory Keywords Power estimation, Model Order Reduction, RCL Interconnect, Moment matching 1. INTRODUCTION As the scale of process technologies steadily shrinks and the size of designs increases, interconnects have increasing impact on the area, delay, and power consumption of circuits. Over the past decade there have been a number of advances in modeling and the analysis of interconnect that have facilitated the continual advances in design automation for systems of increasing size and frequency. As integrated circuit feature sizes continue to scale well below 0.18 µm [2], active device counts are reaching hundreds of millions. Interconnect models must incorporate distributed self and mutual inductance to accurately estimate time delay and crosstalk in a multilevel network for multi-GHz gigascale integration (GSI) [3]. In addition to interconnect delay, crosstalk noise resulting from capacitive and, more recently investigated, inductive effects [4], [5] between adjacent interconnect lines is also becoming a primary concern for ICs performance and reliability. Furthermore, with present VLSI technology, on -chip interconnects are best modeled as a network of coupled lines the amount of interconnect among the devices tends to grow super linearly with the transistor counts, and the chip area is often limited by the physical interconnect area. Due to these interconnect area limitations, the interconnect dimensions are scaled with the devices whenever possible. In addition, to provide more wiring resources, IC’s now accommodate numerous metallization layers, with more to come in the future. These advances in technology that result in scaled, multi-level interconnects may address the wire ability problem, but in the process create problems with signal integrity and interconnect delay. As regards power, the situation is similar in that the portion of power associated with interconnects is increasing. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. Furthermore, the power consumed by interconnects results in a phenomenon, called self heating, which reduces electro-migration induced mean time to failure (MTF) [6]. It is shown in [7] that the power distribution analysis on interconnects is feasible in frequency domain using poles and residues. However, high complexity is inevitable when calculating the power dissipation of the whole interconnects since poles and residues of the current flowing through each element have to be calculated. As feature sizes are decreased to deep sub-micrometer dimensions, on-chip interconnect is best modeled as a distributed RLC line. However, unlike the RC model, such a model increases the complexity of interconnects crosstalk noise and its induced delay estimation. Advances in deep sub-micron technology indicate that present and future interconnects might no longer be considered as simply made of RC lines. Thus, RLC interconnect models become a necessity [8]. It therefore appears that, if accurate interconnect delay estimation is to be achieved, modeling interconnect as a distributed RLC line is necessary. In this case, the commonly and generally well-accepted Elmore delay calculation becomes inapplicable to RLC interconnect networks due to their non-monotonic characteristics induced by inductances [8] [9]. To verify the effects induced by interconnects a combination of extraction and analysis is necessary. Extraction determines the capacitance and the resistance of interconnects, which can then be used to build a circuit model for the analysis of interconnect effects. For analysis (or estimation), extensive studies have been made of the use of model order reduction over the last few years, following the introduction of AWE [9]. Model order reduction is based on approximating the Laplace-domain transfer function of a linear network by a relatively small number of dominant poles and zeros. Such reduced order models can be used to predict the timedomain or frequency-domain response of the linear network. Power, which inherently involves improper integration, can be derived from the poles and residues of the transfer function, which requires only algebraic computation. When the interconnect is driven by MOSFETs and connected to the gates of MOSFETs, the

In modern digital systems, on-chip interconnects have become the system bottleneck, limiting the performance of high-speed clock distributions and data communications in terms of speed and power dissipation. An inverse signaling analysis is developed to optimize the driving signal waveforms for lossy interconnects. By specifying the performance parameters, i.e., the signal swing and edge rate of the interconnect output signal, the corresponding input signals can be derived analytically. The result can be used to guide and optimize the design of interconnect preemphasis drivers. Numerical examples are shown for both lossy RC and RLC distributed lines. Analysis shows that optimized driving voltage and current can increase the interconnect bandwidth without voltage overshoot at the output. The significance of an interconnect inductance is also evaluated with this technique.

The implementation of interconnect is becoming a significant challenge in modern integrated circuit (IC) design. Both synchronous and asynchronous strategies have been suggested to manage this problem. Creating a low skew clock tree for synchronous inter-block pipeline stages is a significant challenge. Asynchronous interconnect does not require a global clock, and therefore, it has a potential advantage in terms of design effort. This paper presents an asynchronous interconnect design that can be implemented using a standard application-specific IC flow. This design is considered across a range of IC interconnect scenarios. The results demonstrate that there is a region of the design space where the implementation provides an advantage over a synchronous interconnect by removing the need for clocked inter-block pipeline stages, while maintaining high throughput. Further results demonstrate a computer-aided design tool enhancement that would significantly increase this space. A detailed comparison of power, area, and latency of the two strategies is also provided for a range of IC scenarios.

A significant performance limitation in integrated circuits has become the metal interconnect, which is responsible for depressing the on-chip data bandwidth while consuming an increasing percentage of power. These problems will grow as wire diameters scale down and the resistance-capacitance product of the interconnect wires increases hyperbolically, which threatens to choke off the computational performance increases of chips that we have come to expect over time. We examine some of the quantitative implications of these trends by analyzing the International Technology Roadmap for Semiconductors. We compare the potential of replacing the global electronic interconnect of future chips with a photonic interconnect and see that there is in principle a four order of magnitude bandwidth-to-power ratio advantage for the latter. This indicates that it could be possible to dramatically improve chip performance without scaling transistors but rather utilize the capability of existing transistors much more efficiently. However, at this time it is not clear if these advantages can be realized. We discuss various issues related to the architecture and components necessary to implement on-chip photonic interconnect.

Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect in the past two decades. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one tenth of the chip edge length at the 22 nm technology node.

As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.

Technology scaling makes designers face difficulties dealing with wire delay of long global interconnects, especially for high-radix networks. In this context, we propose decentralization of on-chip packet routers. A decentralized router consists of submodules, each of which has particular functionality and they are scattered on a link, thereby long wires are segmented. Our starting point is from a conventional router architecture, and we illustrate four case studies to generalize our proposal. We also propose a new buffer design and how to balance pipelines of a router. A proof-of-concept is shown in 28-nm process technology. Our results demonstrate that the decentralization of an on-chip router enables Link Traversal (LT) stages to be eliminated, and the critical path delay is improved by up to 45% with the reduced area compared with a conventional router. As technology advances, the benefit of the decentralized routers become more substantial in the nano-scale era.

FPGA interconnect traditionally dominates energy and delay, and designs such as low-swing interconnect have been proven to reduce the interconnect burden for low energy FPGAs. This paper presents an optimized low-swing interconnect for FPGAs operating in the sub-threshold region. We also address signal degradation along lengthy interconnect paths and examine strategies for inserting low-switching-threshold repeaters. A 130nm test chip implementing low-swing interconnect meshes with different circuit parameters is measured. The results show that optimization of the low-swing interconnect provides up to 60.2% lower energy-delay-product (EDP) than a straightforward, un-optimized low-swing design at V DD = 0.4V. Furthermore, the simulation results show that the optimized low-swing interconnect is 97.7% faster and 42.7% lower energy than a traditional uni-directional interconnect at V DD = 0.4V.

While traditional transistor scaling in integrated circuit industry is going on one side, interconnect scaling has become the performance-limiting factor for new designs on the other side. The increasing influence of interconnect parasites on crosstalk noise and RLC delay as well as electro-migration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Additionally, entirely new technology such as optical interconnect is required to address future global routing needs and sustain performance improvement.

Conventional CMOS technology is reaching fundamental scaling limits, and interconnection bottleneck is dominating IC power and performance. Migrating to 3-D integrated circuits, though promising, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Skybridge, a fine-grained 3-D IC fabric technology was recently proposed towards this aim, which offers a paradigm shift in technology scaling and design. In this paper we present specifically architected core Skybridge structures to enable fine-grained connectivity in 3-D intrinsically. We develop predictive models for interconnect length distribution for Skybridge, and use them to quantify the benefits in terms of expected reduction in interconnect lengths and repeater counts when compared to 2-D CMOS in 16nm node. Our estimation indicates up to 10x reduction in longest global interconnect length vs. 16nm 2-D CMOS, and up to 2 orders of magnitude reduction in the number of repeaters for a design consisting of 10 million logic gates. These results show great promise in alleviating interconnect bottleneck due to a higher degree of connectivity in 3-D, leading to shorter global interconnects and reduced power and area overhead due to repeater insertion.

Multiple cores are preferred to meet the ever increasing computation demand of embedded systems. A multi-core system is communication intensive with on-chip wire delays and on-chip interconnects accounting for half the dynamic power dissipation. A three-dimensional (3D) stacking of dies enables low intra-chip distances for signal transmission and helps to overcome the interconnect bottleneck of multi-core systems. The 3D integration by through silicon via (TSV) can significantly improve memory-logic communication bandwidth of multi-core systems. However, the 3D multi-core system has poor heat removal capability due to position of the heat-sink. In this paper, we made a study on the thermal profile of DRAM memory layers of 3-D multi-core system. In this study, workloads are distributed to memory layers based on its thermal efficiency such that work load of heavier applications is allocated to the memory layer having highest thermal efficiency and those of lighter applications is allocated to the memory layer with lower thermal efficiency. Experimental result shows that with selective work load distribution, the average peak temperature of the 3D multi-core system is reduced than randomly allocated work load to the memory layers. A memory controller could be designed for run-time distribution of work load to the memory layers which will be addressed in the future work.

Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Generating tests to detect such defects is challenging due to the need to accurately determine the coupling capacitances between the open net and its aggressors and fix the state of these aggressors during test. Process variations cause deviations from assumed values of circuit parameters thus potentially invalidating tests generated with assumed circuit parameters. Additionally, recent investigation using test chips showed that the steady state voltage on open nets may drift slowly with the application of circuit inputs and can be different at different nets.

Photonic Networks-on-Chip (PNoCs) have emerged as an auspicious solution to solve the interconnect bottleneck found in their electronic counterparts. Thanks to their low-power properties and the tremendous achieved throughput, PNoCs are presented as highly scalable architectures that can satisfy the requirements of future generation many-core systems. In conventional hybrid PNoC systems, the path-setup algorithm determines the route and the required resources necessary for the end-to-end optical data transfer. Thus, this algorithm should be carefully designed as it plays a crucial role in determining the performance and power efficiency of such systems. In this paper, we present a contention-free routing for photonic mesh-based network-on-chip systems. The algorithm allows data and control/configuration signals to be transferred in the optical network. When implemented on our PHENIC-II system, evaluation results show that the End-to-End (ETE) latency is reduced by 40% and the overall energy of the electronic control module is reduced by 23% when compared to conventional hybrid PNoC systems.