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Synthetic genetic devices can perform molecular computation in living bacteria, which may sense more than one environmental chemical signal, perform complex signal processing in a human-designed way, and respond in a logical manner. IMPLY is one of the four fundamental logic functions and unlike others, it is an "IF-THEN" constraint-based logic. By adopting physical hierarchy of electronics in the realm of in-cell systems chemistry, a full-spectrum transcriptional cascaded synthetic genetic IMPLY gate, which senses and integrates two environmental chemical signals, is designed, fabricated, and optimized in a single Escherichia coli cell. This IMPLY gate is successfully integrated into a 2-input-2-output integrated logic circuit and showed higher signal-decoding efficiency. Further, we showed simple application of those devices by integrating them with an inherent cellular process, where we controlled the cell morphology and color in a logical manner. To fabricate and optimize the genetic devices, a new process pipeline named NETWORK Brick is developed. This pipeline allows fast parallel kinetic optimization and reduction in the unwanted kinetic influence of one DNA module over another. A mathematical model is developed and it shows that response of the genetic devices are digital-like and are mathematically predictable. This single-cell IMPLY gate provides the fundamental constraint-based logic and completes the in-cell molecular logic processing toolbox. The work has significance in the smart biosensor, artificial in-cell molecular computation, synthetic biology, and microbiorobotics.

In this work we present a memristor emulator that allows implementation in a purely digital environment. The emulator is based on a flux-charge description of the memristor, as proposed in the literature. It has been implemented in a commercial FPGA, and it has been shown that its behaviour mimics that of a circuit using memristors. Specifically, we show that it reproduces the fingerprints of a memristor, both in frequency and memory capability. In addition, we also reproduce an IMPLY gate, showing that the behaviour is correctly reproduced.

In the last years, memristor devices have been proposed as key elements to develop a new paradigm to implement logic gates. In particular, the memristor-based material implication (IMPLY) gate has been presented as a potential powerful basis for logic applications. In the literature, the IMPLY operation has been widely simulated, but most of the efforts have been just focused on accomplishing its truth table, only considering the initial and final states of the gate. However, a complete understanding of the time evolution between states is still missing and barely reported yet. In this paper, the time evolution of the memristors involved in an IMPLY gate are studied in detail for every case of the gate. Furthermore, the impact on IMPLY gate operation of the internal resistor connected in series with the memristors of the IMPLY gate is included.

Memristor based modulo multipliers for radix (2n − 1) and 2n have been reported in this paper. Memristor technology is an emerging field in the processor design technology. Here the functional components of the proposed multiplier structures such as partial products, adder etc. have been designed using IMPLY gate which is the first building block implemented using memristor. In memristive logic family, each memristor acts as an input, output, computational logic element in computation process. The main contribution of this paper is to show the design methodologies for modulo multiplication for (2n − 1) and 2n radix and then the techniques has been implemented using memristor. The modulo multiplication schemes, which have been presented here, have generic structures for n bit with radix (2n − 1) and 2n. We have calculated the memristor count to estimate the latency of the design.

Memristors can be used as logic gates. No design methodology exists, however, for memristor-based combinatorial logic. In this paper, the design and behavior of a memristive-based logic gate - an IMPLY gate - are presented and design issues such as the tradeoff between speed (fast write times) and correct logic behavior are described, as part of an overall design methodology. A memristor model is described for determining the write time and state drift. It is shown that the widely used memristor model - a linear ion drift memristor - is impractical for characterizing an IMPLY logic gate, and a different memristor model is necessary such as a memristor with a current threshold.